introduce verilog_sva_property_typet

This introduces a type for Verilog SVA properties To distinguish properties
from state predicates and sequences.

Author: kroening

src/hw_cbmc_irep_ids.h

@@ -140,6 +140,7 @@ IREP_ID_ONE(verilog_null)
 IREP_ID_ONE(verilog_event)
 IREP_ID_ONE(verilog_event_trigger)
 IREP_ID_ONE(verilog_string)
+IREP_ID_ONE(verilog_sva_property)
 IREP_ID_ONE(verilog_sva_sequence)
 IREP_ID_ONE(reg)
 IREP_ID_ONE(macromodule)

src/verilog/verilog_types.h

@@ -739,6 +739,15 @@ inline verilog_package_scope_typet &to_verilog_package_scope_type(typet &type)
   return static_cast<verilog_package_scope_typet &>(type);
 }
 
+/// SVA properties
+class verilog_sva_property_typet : public typet
+{
+public:
+  verilog_sva_property_typet() : typet(ID_verilog_sva_property)
+  {
+  }
+};
+
 /// SVA sequences
 class verilog_sva_sequence_typet : public typet
 {