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Merge pull request #246 from diffblue/simplify_reduction_or
Verilog: simplify reduction_or
2 parents 3a1183a + 302ad8b commit 9cfceac

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src/verilog/verilog_typecheck_expr.cpp

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@@ -1250,6 +1250,14 @@ exprt verilog_typecheck_exprt::elaborate_constant_expression(exprt expr)
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if(!operands_are_constant)
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return expr; // give up
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if(expr.id() == ID_reduction_or)
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{
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// The simplifier doesn't know how to simplify reduction_or
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auto &reduction_or = to_unary_expr(expr);
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expr = notequal_exprt(
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reduction_or.op(), from_integer(0, reduction_or.op().type()));
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}
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// We fall back to the simplifier to approximate
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// the standard's definition of 'constant expression'.
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return simplify_expr(expr, ns);

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