Merge pull request #597 from diffblue/assignment-tests

Assignment tests

Author: tautschnig

regression/verilog/assignment-to-concatenation/test.desc renamed to regression/verilog/assignments/assignment-to-concatenation1.desc

@@ -1,5 +1,5 @@
 CORE broken-smt-backend
-main.v
+assignment-to-concatenation1.v
 --bound 1
 ^EXIT=0$
 ^SIGNAL=0$

regression/verilog/assignment-to-concatenation/main.v renamed to regression/verilog/assignments/assignment-to-concatenation1.v

@@ -1,5 +1,5 @@
 CORE broken-smt-backend
-main.v
+assignment-to-index1.v
 --bound 1
 ^EXIT=0$
 ^SIGNAL=0$

regression/verilog/assignment-to-range1/test.desc renamed to regression/verilog/assignments/assignment-to-index1.desc

@@ -1,5 +1,5 @@
 KNOWNBUG
-main.sv
+assignment-with-function-call1.sv
 --bound 1
 ^EXIT=0$
 ^SIGNAL=0$

regression/verilog/assignment-to-range1/main.v renamed to regression/verilog/assignments/assignment-to-index1.v

@@ -0,0 +1,9 @@
+KNOWNBUG
+procedural_assignments1.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The += assignment is broken.

regression/verilog/assignment-with-function-call/test.desc renamed to regression/verilog/assignments/assignment-with-function-call1.desc

@@ -0,0 +1,56 @@
+module main(input [31:0] in);
+
+  reg [31:0] data;
+
+  always @in begin
+    data = 1;
+    a01: assert(data == 1);
+
+    data++;
+    a02: assert(data == 2);
+
+    data--;
+    a03: assert(data == 1);
+
+    data <= in; // non-blocking
+    a04: assert(data == 1);
+
+    data += 10;
+    a05: assert(data == 11);
+
+    data -= 10;
+    a06: assert(data == 1);
+
+    data *= 5;
+    a07: assert(data == 5);
+
+    data /= 2;
+    a08: assert(data == 2);
+
+    data %= 3;
+    a09: assert(data == 2);
+
+    data &= 3;
+    a10: assert(data == 2);
+
+    data |= 1;
+    a11: assert(data == 3);
+
+    data ^= 1;
+    a12: assert(data == 2);
+
+    data <<= 1;
+    a13: assert(data == 4);
+
+    data >>= 1;
+    a14: assert(data == 2);
+
+    data <<<= 1;
+    a15: assert(data == 4);
+
+    data >>>= 1;
+    a16: assert(data == 2);
+
+  end
+
+endmodule