Verilog: KNOWNBUG test for continuous assignment to part select of net

This reproduces issue #638.

Author: kroening

regression/verilog/synthesis/continuous_assignment_to_net_part_select1.desc

@@ -0,0 +1,7 @@
+KNOWNUG
+continuous_assignment_to_net_part_select1.sv
+--bound 0
+^\[main\.p0\] always main\.some_wire\[1:0\] == 1: PROVED up to bound 0$
+^EXIT=0$
+^SIGNAL=0$
+--