Verilog: KNOWNBUG test for parameter in port binding

The parameter is not expanded to its value in the port binding.

Author: kroening

regression/verilog/modules/ports4.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+ports4.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The parameter in the module instance port binding is not expanded.

regression/verilog/modules/ports4.v

@@ -0,0 +1,13 @@
+module submodule(input [7:0] data);
+
+  always assert p0: data == 123;
+
+endmodule
+
+module main#(parameter MY_PARAMETER = 123)();
+
+  submodule instance(MY_PARAMETER);
+
+  always assert p1: MY_PARAMETER == 123;
+
+endmodule