Merge pull request #604 from diffblue/nested_modules

SystemVeriliog: KNOWNBUG test for nested modules

Author: tautschnig

regression/verilog/modules/nested1.desc

@@ -0,0 +1,6 @@
+KNOWNBUG
+nested1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--

regression/verilog/modules/nested1.sv

@@ -0,0 +1,11 @@
+module main;
+
+  module my_module;
+    wire [7:0] value = 123;
+  endmodule
+
+  my_module m();
+
+  assert final (m.value == 123);
+
+endmodule