SVA Monitors

This adds an alternative flow for checking SVA properties, by translating
the property into a monitor, which is added to the transition system.

Author: kroening

regression/ebmc/sva-monitor/always1.desc

@@ -0,0 +1,13 @@
+CORE
+always1.sv
+--sva-monitor --smv-word-level
+^VAR initial : boolean;$
+^VAR always_activated : boolean;$
+^INIT sva-monitor::initial$
+^INIT !sva-monitor::always_activated$
+^TRANS !next\(sva-monitor::initial\)$
+^TRANS next\(sva-monitor::always_activated\) = sva-monitor::always_active$
+^LTLSPEC G \(sva-monitor::always_active -> FALSE\)$
+^EXIT=0$
+^SIGNAL=0$
+--

regression/ebmc/sva-monitor/always1.sv

@@ -0,0 +1,5 @@
+module main(input clk);
+
+  p0: assert property (0);
+
+endmodule

regression/ebmc/sva-monitor/initial1.desc

@@ -0,0 +1,6 @@
+CORE
+initial1.sv
+--sva-monitor --smv-word-level
+^EXIT=0$
+^SIGNAL=0$
+--

regression/ebmc/sva-monitor/initial1.sv

@@ -0,0 +1,5 @@
+module main(input clk);
+
+  initial p0: assert property (0);
+
+endmodule

regression/ebmc/sva-monitor/s_eventually1.desc

@@ -0,0 +1,7 @@
+CORE
+s_eventually1.sv
+--sva-monitor --smv-word-level
+^-- Verilog::main\.p0: not converted$
+^EXIT=0$
+^SIGNAL=0$
+--

regression/ebmc/sva-monitor/s_eventually1.sv

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+module main(input clk);
+
+  p0: assert property (s_eventually 0);
+
+endmodule

regression/ebmc/sva-monitor/s_nexttime1.desc

@@ -0,0 +1,13 @@
+CORE
+s_nexttime1.sv
+--sva-monitor --smv-word-level
+^VAR initial : boolean;$
+^VAR delayed_active : boolean;$
+^INIT sva-monitor::initial$
+^INIT !sva-monitor::delayed_active$
+^TRANS !next\(sva-monitor::initial\)$
+^TRANS next\(sva-monitor::delayed_active\) = sva-monitor::initial$
+^LTLSPEC G \(sva-monitor::delayed_active -> FALSE\)$
+^EXIT=0$
+^SIGNAL=0$
+--

regression/ebmc/sva-monitor/s_nexttime1.sv

@@ -0,0 +1,5 @@
+module main(input clk);
+
+  initial p0: assert property (s_nexttime 0);
+
+endmodule

regression/ebmc/sva-monitor/sequence1.desc

@@ -0,0 +1,6 @@
+CORE
+sequence1.sv
+--sva-monitor --smv-word-level
+^EXIT=0$
+^SIGNAL=0$
+--

regression/ebmc/sva-monitor/sequence1.sv

@@ -0,0 +1,10 @@
+module main(input clk);
+
+  reg [31:0] x = 0;
+
+  always_ff @(posedge clk)
+    x++;
+
+  initial p0: assert property (x==0 ##1 x==1 ##1 x==2);
+
+endmodule