Merge pull request #655 from diffblue/signed2

Verilog: KNOWNBUG test for signed base 2 literal

Author: tautschnig

regression/verilog/expressions/signed2.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+signed2.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The signed base 2 literal should be sign-extended.

regression/verilog/expressions/signed2.sv

@@ -0,0 +1,7 @@
+module main;
+
+  p0: assert final ('sb1 == -1);
+  p1: assert final ('sb11 == -1);
+  p2: assert final (4'sb111 == 7);
+
+endmodule