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Merge pull request #317 from diffblue/preprocess-I
Verilog: --preprocess now honors -I
2 parents 987dfd2 + c1dd414 commit 445ab39

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CORE
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include2.v
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--preprocess -I subdir
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// Enable multi-line checking
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activate-multi-line-match
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`line 1 "include2\.v" 0
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`line 1 "include_file\.vh" 1
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`line 2 "include2\.v" 2
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^EXIT=0$
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^SIGNAL=0$
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--
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`include "include_file.vh"
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src/ebmc/transition_system.cpp

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@@ -92,6 +92,10 @@ int preprocess(const cmdlinet &cmdline, message_handlert &message_handler)
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return 1;
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}
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// do -I
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if(cmdline.isset('I'))
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config.verilog.include_paths = cmdline.get_values('I');
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auto language = get_language_from_filename(filename);
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if(language == nullptr)

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