SystemVerilog: interface instantiation

Author: kroening

regression/verilog/interface/interface1.sv

@@ -2,4 +2,5 @@ interface myInterface;
 endinterface
 
 module main;
+  myInterface some_interface;
 endmodule

src/verilog/parser.y

@@ -986,6 +986,7 @@ port_direction:
 
 module_common_item:
           module_or_generate_item_declaration
+        | interface_instantiation
         | assertion_item
         | bind_directive
 	| continuous_assign
@@ -3021,6 +3022,16 @@ named_port_connection:
                   mto($$, $4); }
 	;
 
+hierarchical_instance: name_of_instance
+	;
+
+// System Verilog standard 1800-2017
+// A.4.1.2 Interface instantiation
+
+interface_instantiation:
+	  interface_identifier hierarchical_instance ';'
+	;
+
 // System Verilog standard 1800-2017
 // A.4.2 Generated instantiation