Merge pull request #844 from diffblue/instrument_past

Instrumentation for `$past`

Author: kroening

CHANGELOG

@@ -2,6 +2,7 @@
 
 * Verilog: bugfix for $onehot0
 * Verilog: fix for primitive gates with more than two inputs
+* Verilog: Support $past when using AIG-based engines
 
 # EBMC 5.4
 

regression/verilog/system-functions/past-instrumentation1.desc

@@ -0,0 +1,8 @@
+CORE
+past-instrumentation1.sv
+--bound 10 --aig
+^\[.*\] always main\.counter >= 1 -> \$past\(main\.counter, 1\) == main\.counter - 1: PROVED up to bound 10$
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/system-functions/past-instrumentation1.sv

@@ -0,0 +1,18 @@
+module main(input clk);
+
+  reg [31:0] counter = 0;
+
+  always @(posedge clk)
+    counter++;
+
+  assert property ($past(counter, 0) == counter);
+
+  assert property (counter >= 1 -> $past(counter, 1) == counter - 1);
+
+  assert property (counter >= 2 -> $past(counter, 2) == counter - 2);
+
+  assert property (counter == 0 -> $past(counter, 1) == 0);
+
+  assert property (counter == 1 -> $past(counter, 2) == 0);
+
+endmodule

regression/verilog/system-functions/past-instrumentation2.desc

@@ -0,0 +1,12 @@
+CORE
+past-instrumentation2.sv
+--bdd
+\[main\.assert\.1\] always \$past\(main\.counter, 0\) == main\.counter: PROVED$
+\[main\.assert\.2\] always main\.counter >= 1 -> \$past\(main\.counter, 1\) == main\.counter - 1: PROVED$
+\[main\.assert\.3\] always main\.counter >= 2 -> \$past\(main\.counter, 2\) == main\.counter - 2: PROVED$
+\[main\.assert\.4\] always main\.counter == 0 -> \$past\(main\.counter, 1\) == 0: REFUTED$
+\[main\.assert\.5\] always main\.counter == 1 -> \$past\(main\.counter, 2\) == 0: REFUTED$
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/system-functions/past-instrumentation2.sv

@@ -0,0 +1,20 @@
+module main(input clk);
+
+  reg [3:0] counter = 0;
+
+  always @(posedge clk)
+    counter++;
+
+  assert property ($past(counter, 0) == counter);
+
+  assert property (counter >= 1 -> $past(counter, 1) == counter - 1);
+
+  assert property (counter >= 2 -> $past(counter, 2) == counter - 2);
+
+  // expected to fail -- the counter can wrap around
+  assert property (counter == 0 -> $past(counter, 1) == 0);
+
+  // expected to fail -- the counter can wrap around
+  assert property (counter == 1 -> $past(counter, 2) == 0);
+
+endmodule

regression/verilog/system-functions/past-instrumentation3.desc

@@ -0,0 +1,8 @@
+CORE
+past-instrumentation3.sv
+--bdd
+\[.*\] always main\.counter >= 2 -> \$past\(main\.counter, 2\) == main\.counter - 2: PROVED$
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/system-functions/past-instrumentation3.sv

@@ -0,0 +1,11 @@
+module main(input clk);
+
+  reg [3:0] counter = 0;
+
+  always @(posedge clk)
+    counter++;
+
+  // $past(counter, 1) is deliberately not used
+  assert property (counter >= 2 -> $past(counter, 2) == counter - 2);
+
+endmodule

regression/verilog/system-functions/past2.desc

@@ -1,8 +1,8 @@
 CORE
 past2.sv
 --bdd
-^\[main\.p0\] always \(main\.counter == 0 \|-> \$past\(main\.counter, 1\) == 0\): FAILURE: property not supported by BDD engine$
-^EXIT=10$
+^\[main\.p0\] always \(main\.counter == 0 \|-> \$past\(main\.counter, 1\) == 0\): PROVED$
+^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring

regression/verilog/system-functions/past2.sv

@@ -1,12 +1,12 @@
 module main(input clk);
 
-  reg [31:0] counter = 0;
+  reg [3:0] counter = 0;
 
   always @(posedge clk)
     if(counter < 10)
       counter++;
 
   p0: assert property (counter == 0 |-> $past(counter, 1) == 0);
-//  p1: assert property (counter != 0 && counter != 10 |-> $past(counter, 1) == counter - 1);
+  p1: assert property (counter != 0 && counter != 10 |-> $past(counter, 1) == counter - 1);
 
 endmodule

src/ebmc/Makefile

@@ -15,6 +15,7 @@ SRC = \
       ebmc_parse_options.cpp \
       ebmc_properties.cpp \
       ebmc_solver_factory.cpp \
+      instrument_past.cpp \
       k_induction.cpp \
       liveness_to_safety.cpp \
       live_signal.cpp \