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lines changed Original file line number Diff line number Diff line change 1
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CORE
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counter1
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- ^weight main. clk = 0 .*$
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- ^weight main. counter = 1 .*$
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- ^RESULT: main.counter-1 $
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- ^bias: -1 .* $
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+ ^weight clk = 0 .*$
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+ ^weight counter = 1 .*$
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+ ^bias: 0 .* $
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+ ^RESULT: counter $
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^EXIT=0$
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^SIGNAL=0$
Original file line number Diff line number Diff line change @@ -6,6 +6,6 @@ module main(input clk);
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if (counter != 0 )
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counter = counter - 1 ;
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- wire \nuterm:: live = counter == 0 ;
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+ wire \$ live = counter == 0 ;
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endmodule
Original file line number Diff line number Diff line change 1
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$date
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- Mon May 20 14:40:33 2024
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+ Mon May 20 17:39:58 2024
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$end
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$timescale
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1ns
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$end
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$scope module Verilog::main $end
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$var wire 1 main.clk clk $end
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$var reg 32 main.counter counter [31:0] $end
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- $var wire 1 main.nuterm:: live nuterm:: live $end
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+ $var wire 1 main.$ live $ live $end
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$upscope $end
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$enddefinitions $end
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#0
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0main.clk
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b00010000000000000000000000000000 main.counter
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- 0main.nuterm:: live
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+ 0main.$ live
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#1
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1main.clk
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b00001111111111111111111111111111 main.counter
Original file line number Diff line number Diff line change 1
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$date
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- Mon May 20 14:40:33 2024
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+ Mon May 20 17:39:58 2024
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$end
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$timescale
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1ns
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$end
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$scope module Verilog::main $end
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$var wire 1 main.clk clk $end
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$var reg 32 main.counter counter [31:0] $end
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- $var wire 1 main.nuterm:: live nuterm:: live $end
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+ $var wire 1 main.$ live $ live $end
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$upscope $end
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$enddefinitions $end
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#0
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0main.clk
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b00010000000000000000000000000000 main.counter
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- 0main.nuterm:: live
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+ 0main.$ live
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#1
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1main.clk
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b00001111111111111111111111111111 main.counter
Original file line number Diff line number Diff line change 1
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$date
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- Mon May 20 14:40:33 2024
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+ Mon May 20 17:39:58 2024
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$end
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$timescale
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1ns
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$end
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$scope module Verilog::main $end
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$var wire 1 main.clk clk $end
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$var reg 32 main.counter counter [31:0] $end
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- $var wire 1 main.nuterm:: live nuterm:: live $end
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+ $var wire 1 main.$ live $ live $end
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$upscope $end
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$enddefinitions $end
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#0
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0main.clk
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b00010000000000000000000000000000 main.counter
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- 0main.nuterm:: live
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+ 0main.$ live
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#1
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b00001111111111111111111111111111 main.counter
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#2
Original file line number Diff line number Diff line change 1
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$date
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- Mon May 20 14:40:33 2024
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+ Mon May 20 17:39:58 2024
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$end
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$timescale
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1ns
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$end
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$scope module Verilog::main $end
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$var wire 1 main.clk clk $end
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$var reg 32 main.counter counter [31:0] $end
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- $var wire 1 main.nuterm:: live nuterm:: live $end
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+ $var wire 1 main.$ live $ live $end
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$upscope $end
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$enddefinitions $end
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#0
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1main.clk
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b00010000000000000000000000000000 main.counter
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- 0main.nuterm:: live
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+ 0main.$ live
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#1
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0main.clk
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b00001111111111111111111111111111 main.counter
Original file line number Diff line number Diff line change 1
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$date
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- Mon May 20 14:40:33 2024
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+ Mon May 20 17:39:58 2024
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$end
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$timescale
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1ns
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$end
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$scope module Verilog::main $end
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$var wire 1 main.clk clk $end
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$var reg 32 main.counter counter [31:0] $end
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- $var wire 1 main.nuterm:: live nuterm:: live $end
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+ $var wire 1 main.$ live $ live $end
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$upscope $end
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$enddefinitions $end
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#0
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0main.clk
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b00010000000000000000000000000000 main.counter
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- 0main.nuterm:: live
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+ 0main.$ live
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#1
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1main.clk
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b00001111111111111111111111111111 main.counter
Original file line number Diff line number Diff line change 1
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$date
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- Mon May 20 14:40:33 2024
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+ Mon May 20 17:39:58 2024
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$end
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$timescale
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1ns
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$end
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$scope module Verilog::main $end
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$var wire 1 main.clk clk $end
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$var reg 32 main.counter counter [31:0] $end
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- $var wire 1 main.nuterm:: live nuterm:: live $end
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+ $var wire 1 main.$ live $ live $end
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$upscope $end
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$enddefinitions $end
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#0
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1main.clk
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b00010000000000000000000000000000 main.counter
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- 0main.nuterm:: live
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+ 0main.$ live
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#1
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b00001111111111111111111111111111 main.counter
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#2
Original file line number Diff line number Diff line change 1
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$date
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- Mon May 20 14:40:33 2024
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+ Mon May 20 17:39:58 2024
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$end
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$timescale
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1ns
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$end
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$scope module Verilog::main $end
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$var wire 1 main.clk clk $end
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$var reg 32 main.counter counter [31:0] $end
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- $var wire 1 main.nuterm:: live nuterm:: live $end
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+ $var wire 1 main.$ live $ live $end
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$upscope $end
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$enddefinitions $end
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#0
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0main.clk
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b00010000000000000000000000000000 main.counter
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- 0main.nuterm:: live
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+ 0main.$ live
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#1
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1main.clk
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b00001111111111111111111111111111 main.counter
Original file line number Diff line number Diff line change 1
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$date
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- Mon May 20 14:40:33 2024
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+ Mon May 20 17:39:58 2024
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$end
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$timescale
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1ns
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$end
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$scope module Verilog::main $end
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$var wire 1 main.clk clk $end
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$var reg 32 main.counter counter [31:0] $end
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- $var wire 1 main.nuterm:: live nuterm:: live $end
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+ $var wire 1 main.$ live $ live $end
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$upscope $end
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$enddefinitions $end
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#0
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0main.clk
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b00010000000000000000000000000000 main.counter
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- 0main.nuterm:: live
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+ 0main.$ live
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#1
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b00001111111111111111111111111111 main.counter
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#2
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