Improving Verilog support in FUGen and adding RFGen

.github/workflows/ci.yml

@@ -7,6 +7,7 @@ on:
   pull_request:
     branches:
       - main
+  workflow_dispatch:
 
 jobs:
   build:
@@ -60,7 +61,8 @@ jobs:
             cmake \
             graphviz \
             bc \
-            ghdl
+            ghdl \
+            iverilog
 
       - name:
         run: |

.gitignore

@@ -77,6 +77,7 @@ openasip/scripts/tce-selftest
 openasip/src/applibs/LLVMBackend/passes/.dirstamp
 openasip/src/applibs/LLVMBackend/passes/buildllvmpass
 openasip/src/bintools/Assembler/tceasm
+openasip/src/bintools/TestGenerator/generatetests
 openasip/src/bintools/BEMGenerator/createbem
 openasip/src/bintools/BEMViewer/viewbem
 openasip/src/bintools/BlocksDisassembler/tpef2pasm

openasip/configure.ac

@@ -1387,6 +1387,7 @@ AC_CONFIG_FILES([
   src/bintools/BEMViewer/Makefile
   src/bintools/Assembler/Makefile
   src/bintools/Disassembler/Makefile
+  src/bintools/TestGenerator/Makefile
   src/bintools/BlocksTranslator/Makefile
   src/bintools/BlocksDisassembler/Makefile
   src/applibs/Scheduler/Selector/Makefile
@@ -1425,6 +1426,7 @@ AC_CONFIG_FILES([
   src/applibs/EPSGenerator/Makefile
   src/applibs/costdb/Makefile
   src/applibs/program/Makefile
+  src/applibs/TestGenerator/Makefile
   src/codesign/Estimator/Makefile
   src/procgen/HDB/Makefile 
   src/procgen/ProGe/Makefile

openasip/data/Makefile.am

@@ -39,6 +39,9 @@ nobase_data_DATA =	$(srcdir)/ProDe/confschema.xsd \
 					$(srcdir)/ProGe/debugger/*.vhdl.tmpl \
 					$(srcdir)/ProGe/*.snippet \
 					$(srcdir)/ProGe/debugger/tb/*.vhdl \
-					$(srcdir)/riscv/*
+					$(srcdir)/riscv/* \
+					$(srcdir)/RFGen/vhdl/*.vhdl \
+					$(srcdir)/RFGen/verilog/*.v
+
 
 EXTRA_DIST = ${nobase_data_DATA}

openasip/data/ProGe/idecompressor.v.tmpl

@@ -25,12 +25,12 @@
 // 2012-04-04  1.0  Vinogradov 
 //////////////////////////////////////////////////////////////////////////////
 
-`timescale 10ns/1ns
 module ENTITY_STR_decompressor
-#(    
-`include "ENTITY_STR_globals_pkg.vh"
-,
+#(
 `include "ENTITY_STR_imem_mau_pkg.vh"
+,
+`include "ENTITY_STR_globals_pkg.vh"
+
 )
 (
     output fetch_en,

openasip/data/ProGe/ifetch.v.tmpl

@@ -25,14 +25,13 @@
 // 2012-04-04  1.0  Vinogradov 
 //////////////////////////////////////////////////////////////////////////////
 
-`timescale 10ns/1ns
 module ENTITY_STR_ifetch 
 #(
+`include "ENTITY_STR_imem_mau_pkg.vh"
+,
 `include "ENTITY_STR_globals_pkg.vh"
 ,
 `include "gcu_opcodes_pkg.vh"
-,
-`include "ENTITY_STR_imem_mau_pkg.vh"
 )
     (
     // program counter in
@@ -76,6 +75,7 @@ module ENTITY_STR_ifetch
 
     integer reset_cntr;
     reg reset_lock;
+    reg mem_en_lock_r;
 
     parameter IFETCH_DELAY=1;
 
@@ -89,28 +89,30 @@ module ENTITY_STR_ifetch
     assign ra_out= return_addr_reg;
     assign fetchblock = instruction_reg;
 
-    assign lock = ~fetch_en | busy;
+    assign lock = ~fetch_en | busy | mem_en_lock_r;
 
     always@(posedge clk or negedge rstx)
-    if(~rstx)
-    begin
+    if (~rstx) begin
+        mem_en_lock_r <= '1;
+    end else begin
+        mem_en_lock_r <= '0;
+    end
+
+    always@(posedge clk or negedge rstx)
+    if (~rstx) begin
         pc_reg          <= 0;
         pc_prev_reg     <= {IMEMADDRWIDTH{1'b0}};
         return_addr_reg <= {IMEMADDRWIDTH{1'b0}};
         instruction_reg <= {IMEMWIDTHINMAUS*IMEMMAUWIDTH{1'b0}};
         reset_cntr      <= 0;
         reset_lock      <= 1'b1;
-    end
-    else
-    begin
-        if( fetch_en && ~lock)
-        begin
+    end else begin
+        if (fetch_en && ~lock) begin
             pc_reg      <= next_pc;
             pc_prev_reg <= pc_reg;
         end
 
-        if(~lock)
-        begin
+        if (~lock) begin
             if( reset_cntr < IFETCH_DELAY )
                 reset_cntr <= reset_cntr + 1;
             else
@@ -124,7 +126,7 @@ module ENTITY_STR_ifetch
             if(ra_load)
                 return_addr_reg <= ra_in;
             else
-            if(pc_load && pc_opcode==IFE_CALL)
+            if (pc_load && pc_opcode==IFE_CALL)
                 // return address transformed to same form as all others addresses
                 // provided as input
                 return_addr_reg <= increased_pc;
@@ -134,9 +136,9 @@ module ENTITY_STR_ifetch
     assign increased_pc = pc_reg + IMEMWIDTHINMAUS;
 
     always@(*)
-    if(pc_load)
+    if (pc_load)
         next_pc = pc_in;
-    else// no branch
+    else // no branch
         next_pc = increased_pc;
 
 endmodule

openasip/data/ProGe/tb/clkgen.v

@@ -0,0 +1,64 @@
+// Copyright (c) 2002-2024 Tampere University.
+//
+// This file is part of TTA-Based Codesign Environment (TCE).
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+// DEALINGS IN THE SOFTWARE.
+//////////////////////////////////////////////////////////////////////////////-
+// Title      : Clock generator
+//////////////////////////////////////////////////////////////////////////////-
+// File       : clkgen.v
+// Author     : Joonas Multanen  <[email protected]>
+// Company    :
+// Created    : 2024-03-22
+// Last update: 2024-03-22
+//////////////////////////////////////////////////////////////////////////////-
+// Description: A 50/50 testbench clock. The clock period is defined by
+//           a generic PERIOD
+//////////////////////////////////////////////////////////////////////////////-
+// Revisions  :
+// Date        Version  Author    Description
+// 2024-03-22  1.0      multanej  Created
+//////////////////////////////////////////////////////////////////////////////-
+
+module clkgen
+#(
+    parameter PERIOD = 10
+)
+(
+    output wire clk,
+    input wire  en
+);
+
+   reg          clk_internal;
+
+initial begin
+   clk_internal <= 0;
+end
+
+always begin
+   if (en) begin
+      #(PERIOD) clk_internal <= ~clk_internal;
+   end else begin
+      clk_internal <= 0;
+   end
+end
+
+assign clk = clk_internal;
+
+endmodule // clkgen

openasip/data/ProGe/tb/imem_arbiter.v

@@ -24,7 +24,6 @@
 // Revisions  :
 // 2012-04-04  1.0  Vinogradov 
 //////////////////////////////////////////////////////////////////////////////
-`timescale 10ns/1ns
 
 module imem_arbiter
 #(

openasip/data/ProGe/tb/legacy_testbench.v.tmpl

@@ -31,7 +31,6 @@
 // Revisions  :
 // 2012-04-04  1.0  Vinogradov 
 //////////////////////////////////////////////////////////////////////////////
-`timescale 1ns/1ns
 
 module testbench
 #(

openasip/data/ProGe/tb/mem_arbiter.v

@@ -24,7 +24,6 @@
 // Revisions  :
 // 2012-04-04  1.0  Vinogradov 
 //////////////////////////////////////////////////////////////////////////////
-`timescale 10ns/1ns
 
 module mem_arbiter
 #(

openasip/data/ProGe/tb/synch_byte_mask_sram.v

@@ -0,0 +1,79 @@
+module synch_byte_mask_sram #(parameter
+    // pragma translate_off
+    init = 1,
+    INITFILENAME = "ram_init",
+    trace = 1,
+    TRACEFILENAME = "dpram_trace",
+    trace_mode = 0,
+    access_trace = 1,
+    ACCESSTRACEFILENAME = "access_trace",
+    // pragma translate_on
+    DATAW = 32,
+    ADDRW = 7)
+(
+    input wire   clk,
+    input wire   [DATAW-1:0] adata,
+    input wire   [ADDRW-1:0] aaddr,
+    input wire   avalid,
+    input wire   awren,
+    input wire   [(DATAW/8)-1:0] astrb,
+    output wire  aready,
+    output wire  rvalid,
+    input wire   rready,
+    output wire  [DATAW-1:0] rdata
+);
+
+parameter DW = DATAW;
+parameter AW = ADDRW;
+parameter DW8 = DW / 8;
+
+reg [DW-1:0] mem_r [0:2**AW-1];
+reg [DW-1:0] q_r;
+reg [DW-1:0] wr_mask;
+
+integer line;
+
+integer k;
+
+//this  initial path can be synthesize by quartus
+ initial
+   if(init)
+     if(INITFILENAME!="")
+       begin
+          $readmemb(INITFILENAME,mem_r);
+          $display("Memory initialized from file %s",INITFILENAME);
+       end
+     else
+       begin
+          for(k=0; k<2**ADDRW; k=k+1)
+            mem_r[k]={DATAW{1'b0}};
+          $display("Memory initialized to zeroes!");
+       end
+
+
+assign line = aaddr;
+
+always @(posedge clk) begin
+    if (avalid && awren) begin
+        mem_r[line] <= (adata & wr_mask) | (mem_r[line] & ~wr_mask);
+        q_r <= (adata & wr_mask) | (mem_r[line] & ~wr_mask);
+    end else if (avalid) begin
+        q_r <= mem_r[line];
+    end
+end
+
+integer i,j;
+always @* begin
+    wr_mask = 0;
+    for (i = 0; i < DW8; i = i + 1) begin
+        for (j = i * 8; j < i * 8 + 8; j = j + 1) begin
+            wr_mask[j] = astrb[i];
+        end
+    end
+end
+
+assign rdata = q_r;
+assign rvalid = 1;
+assign aready = 1;
+
+endmodule

openasip/data/ProGe/tb/synch_dualport_sram.v

@@ -34,7 +34,6 @@
 // 2012-04-04  1.0  Vinogradov
 //////////////////////////////////////////////////////////////////////////////
 
-`timescale 10ns/1ns
 
 module synch_dualport_sram
 #(

openasip/data/ProGe/tb/synch_sram.v

@@ -32,16 +32,17 @@
 // Revisions  :
 // 2012-04-04  1.0  Vinogradov
 //////////////////////////////////////////////////////////////////////////////
-`timescale 10ns/1ns
 
 module synch_sram
 #(
-    parameter init          =1,
-    parameter INITFILENAME  ="ram_init",
-    parameter trace         =1,
+    parameter init          = 1,
+    parameter INITFILENAME  = "ram_init",
+    parameter trace         = 1,
     parameter TRACEFILENAME = "dpram_trace",
     // trace_mode 0: hex, trace_mode 1: integer, trace_mode 2: unsigned
     parameter trace_mode    = 0,
+    parameter access_trace = 1,
+    parameter ACCESSTRACEFILENAME = "access_trace",
     parameter DATAW = 32,
     parameter ADDRW = 7
 )