Cranelift: properly reject unimplemented big-endian loads/stores.

[cfallin]

At some point during the development of the Cranelift backend infrastructure, to properly support big-endian architectures such as s390x, we added explicit endianness flags to MemFlags, which are given to all memory operations (e.g., loads, stores, and atomic ops). In s390x in particular, the backend carefully observes these flags, because a prominent use of Cranelift (as a Wasm backend) requires explicit little-endian behavior and the system is big-endian. However, all of our other supported ISAs are little-endian and so we did not implement explicit checks at the time, instead accepting all loads and stores as an artifact of our little-endian-only origins.

This PR adds explicit conditions to all ISLE rules that lower loads, stores, and atomic ops on x86-64, aarch64, and riscv64 to accept little or "native" (also little) endian operations only. Compilation of a big-endian operation will now result in a compilation error because no ISLE rule will match (no lowering exists). At some later point we could add these lowerings, but for now we at least do not miscompile.

Fixes #10861.

[cfallin]

(Note that the Pulley backend rules appear to have explicit consideration for endianness, so I skipped that backend here.)

[cfallin]

Design note: I could have added checks to more central places in all three backends instead -- namely, Amode construction -- but opted instead to annotate every rule with this predicate, because the information logically belongs to the individual lowerings and if we want to add actual big-endian lowerings in the future, we'll want Amode to work for those too.