feat(tricore): Initial tricore support #242
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The cpu variable from struct addr_space was not being used throughout the code. Signed-off-by: Miguel Silva <[email protected]>
The mmio regions present in the platform description are to be mapped accessible for all address spaces. Signed-off-by: Miguel Silva <[email protected]>
Each architecture needs to implement their access control function. This function is called during the dev init for vms, and is executed instead of the original memory mapping. Signed-off-by: Miguel Silva <[email protected]>
Signed-off-by: Miguel Silva <[email protected]>
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All address spaces now have their unique ID. The only exception is the hypervisor itself that always has ID=0. Signed-off-by: Miguel Silva <[email protected]>
Signed-off-by: Miguel Silva <[email protected]>
Refactored slightly the root pool bitmap base to improve clarity of code Removed the passing of load_addr as argument since it can be defined as a global variable in each arch boot file. Signed-off-by: Daniel Oliveira <[email protected]>
Signed-off-by: Daniel Oliveira <[email protected]>
Signed-off-by: Miguel Silva <[email protected]>
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PR Description
This PR introduces the initial support for Infineon Tricore architectures.
This PR requires #218 to support boot from flash with a non-unified memory model.
The current state of this port supports baremetal and freeRTOS guests in single or multicore setups. At the moment, each guest is given an unique ID, and each core only executes one guest.
The following list shows what is missing: