fixed some bugs in pretty printer, and made port checker pass run on …

…commit and exception blocks

src/main/scala/pipedsl/Main.scala

@@ -72,7 +72,6 @@ object Main {
     val prog = parse(debug = false, printOutput = false, inputFile, outDir, rfLockImpl = rfLockImpl)
 
     try {
-      //val prog = ExceptingToNormal.run(ex_prog)
       // new PrettyPrinter(None).printProgram(prog)
       val pinfo = new ProgInfo(prog)
       MarkNonRecursiveModulePass.run(prog)
@@ -81,8 +80,6 @@ object Main {
       val verifProg = AddCheckpointHandlesPass.run(AddVerifyValuesPass.run(inferredProg))
       val canonProg2 = new CanonicalizePass().run(verifProg)
       val canonProg = new TypeInference(autocast).checkProgram(canonProg2)
-      // new PrettyPrinter(None).printProgram(canonProg)
-
       val basetypes = BaseTypeChecker.check(canonProg, None)
       FunctionConstraintChecker.check(canonProg)
       val nprog = new BindModuleTypes(basetypes).run(canonProg)
@@ -106,9 +103,8 @@ object Main {
       val specChecker = new SpeculationChecker(ctx)
       specChecker.check(recvProg, None)
       val lock_prog = LockOpTranslationPass.run(recvProg)
-      TimingTypeChecker.check(lock_prog, Some(basetypes))
+      TimingTypeChecker.check(lock_prog, Some(basetypes))      
       val exnprog = ExnTranslationPass.run(lock_prog)
-      new PrettyPrinter(None).printProgram(exnprog)
       if (printOutput) {
         val writer = new PrintWriter(outputFile)
         writer.write("Passed")

src/main/scala/pipedsl/common/PrettyPrinter.scala

@@ -60,7 +60,7 @@ class PrettyPrinter(output: Option[File]) {
   def printExnBlock(block: Syntax.ExceptBlock, ident: Int): String = block match
   {
     case ExceptEmpty() => ""
-    case ExceptFull(args, c) => "except(" + args.map((id) => id.v).reduce((acc, elem) => acc + "," + elem) + "):\n" + printCmdToString(c, ident)
+    case ExceptFull(args, c) => "except(" + args.map((id) => id.v).foldLeft("")((acc, elem) => acc + "," + elem) + "):\n" + printCmdToString(c, ident)
   }
 
   def printCircuit(c: Circuit): Unit = pline("circuit {\n" + printCircuitToString(c, 2) + "\n}")
@@ -127,7 +127,7 @@ class PrettyPrinter(output: Option[File]) {
         printExprToString(originalSpec) + " = update(" + specId + ", " + printExprToString(value) + ");"
       case Syntax.ICheck(specId, value) => ins + "check(" + specId + ", " + printExprToString(value) + ");"
       case Syntax.CCheckpoint(h, m) => ins + printExprToString(h) + " <- checkpoint(" + m.v + ");"
-      case Syntax.CExcept(args) => ins + "except(" + args.map(printExprToString).reduce((acc, elem) => acc + ", " + elem) + ");"
+      case Syntax.CExcept(args) => ins + "except(" + args.map(printExprToString).foldLeft("")((acc, elem) => acc + ", " + elem) + ");"
       case _ => "TODO PRINTING COMMAND"
     }
   }

src/main/scala/pipedsl/passes/ExnTranslationPass.scala

@@ -21,7 +21,6 @@ object ExnTranslationPass extends ModulePass[ModuleDef] with ProgPass[Prog]{
 
     val new_m = addExnVars(m)
     new_m.name.typ = m.name.typ
-    print(new_m.body)
     val modified_exnblk = m.except_blk.map(convertExnArgsId)
     createNewStg(new_m.copy(body = new_m.body, commit_blk = new_m.commit_blk, except_blk = modified_exnblk))
   }

src/main/scala/pipedsl/typechecker/PortChecker.scala

@@ -62,7 +62,9 @@ class PortChecker(port_warn :Boolean) extends TypeChecks[Id, (Int, Int)]
         case _ : TModType => modLims.addOne((mod.name, (1, 1)))
         case _ =>
       })
-      val port_map = checkPipe(m.body, emptyEnv())
+      val port_tmp = checkPipe(m.body, emptyEnv())
+      val port_com = if (m.commit_blk.isDefined) { checkPipe(m.commit_blk.get, port_tmp) } else port_tmp;
+      val port_map = checkPipe(m.except_blk.get, port_com);
       if(port_warn)
         port_map.getMappedKeys().foreach(mem =>
           {