Merge branch 'evalFixes' of github.com:apl-cornell/PDL into evalFixes

apl-cornell · Jun 17, 2021 · 4441032 · 4441032
2 parents 1666078 + 80e9ea8
commit 4441032
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Showing 2 changed files with 14 additions and 6 deletions.
diff --git a/src/main/scala/pipedsl/codegen/bsv/BSVSyntax.scala b/src/main/scala/pipedsl/codegen/bsv/BSVSyntax.scala
@@ -67,8 +67,8 @@ object BSVSyntax {
             bsints.getLockHandleType(idsz.get)
           } else bsints.getDefaultLockHandleType
         } else {
-          //re-use the id from the memory
-          mtyp.tparams.last.typ
+          //re-use the rid from the memory
+          mtyp.tparams.find(bv => bv.name == bsints.reqIdName).get.typ
         }
         getLockedMemType(mem, mtyp, lidtyp, limpl, useTypeVars = false, None)
       case TSizedInt(len, unsigned) => BSizedInt(unsigned, len)
@@ -226,9 +226,16 @@ object BSVSyntax {
         } else {
           BVar("_unused_", BNumericType(sz))
        }})
-      //replace last tparam w/ lockidtyp if not using a unique id
-      val tmpparams = if (limpl.useUniqueLockId()) { mtyp.tparams } else { mtyp.tparams.init }
-      val params = (tmpparams :+ BVar("lidtyp", lockIdTyp)) ++ lparams
+      //replace tparam named 'ridtyp' w/ lockidtyp if not using a unique id
+      val newLid = BVar("lidtyp", lockIdTyp)
+      val tmpparams = if (limpl.useUniqueLockId()) {
+        mtyp.tparams :+ newLid
+      } else {
+        mtyp.tparams.map(bv => {
+          if (bv.name == bsints.reqIdName) { newLid } else { bv }
+        })
+      }
+      val params = tmpparams ++ lparams
       BInterface(intName, params)
     }
 

diff --git a/src/main/scala/pipedsl/codegen/bsv/BluespecInterfaces.scala b/src/main/scala/pipedsl/codegen/bsv/BluespecInterfaces.scala
@@ -145,14 +145,15 @@ class BluespecInterfaces(val addrlockmod: Option[String]) {
   private val combMemType = "RegFile"
   private val combMemMod = "mkRegFile"
 
+  val reqIdName = "ridtyp"
 
   def getBaseMemType(isAsync: Boolean, elemSize: Int, addr: BSVType, data: BSVType): BInterface = {
     if (isAsync) {
       //TODO make this type parameterizable
       val reqTyp = getDefaultMemHandleType
       val maskSize = elemSize / 8
       BInterface(asyncMemType, List(BVar("addrtyp", addr), BVar("elemtyp", data),
-        BVar("ridtyp", reqTyp), BVar("nsz", BNumericType(maskSize))))
+        BVar(reqIdName, reqTyp), BVar("nsz", BNumericType(maskSize))))
     } else {
       BInterface(combMemType,  List(BVar("addrtyp", addr), BVar("elemtyp", data)))
     }