Nextifying support in chisel3

chiselFrontend/src/main/scala/chisel3/core/Bits.scala

@@ -5,10 +5,10 @@ package chisel3.core
 import scala.language.experimental.macros
 
 import chisel3.internal._
-import chisel3.internal.Builder.{pushCommand, pushOp, pushDeclass, pushEndorse}
+import chisel3.internal.Builder.{pushCommand, pushOp, pushDeclass, pushEndorse, pushNext}
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform,
-  UIntTransform, MuxTransform, DeclassifyTransform, EndorseTransform}
+  UIntTransform, MuxTransform, DeclassifyTransform, EndorseTransform, NextTransform}
 import chisel3.internal.firrtl.PrimOp._
 // TODO: remove this once we have CompileOptions threaded through the macro system.
 import chisel3.core.ExplicitCompileOptions.NotStrict
@@ -790,6 +790,14 @@ object Endorse {
   }
 }
 
+object Next {
+  def apply[T <: Data](arg: T): T = macro NextTransform.apply[T]
+  def do_apply[T <: Data](arg: T)(implicit sourceInfo: SourceInfo): T = {
+    val dtype = arg.cloneType
+    pushNext(DefNext(sourceInfo, dtype, arg.ref))
+  }
+}
+
 object Mux {
   /** Creates a mux, whose output is one of the inputs depending on the
     * value of the condition.

chiselFrontend/src/main/scala/chisel3/internal/Builder.scala

@@ -218,6 +218,12 @@ private[chisel3] object Builder {
     pushCommand(cmd).id
   }
 
+  def pushNext[ T <: Data](cmd: DefNext[T]): T = {
+    // Bind each element of the returned Data to being a Op
+    Binding.bind(cmd.id, OpBinder(forcedModule), "Error: During op creation, fresh result")
+    pushCommand(cmd).id
+  }
+
   def errors: ErrorLog = dynamicContext.errors
   def error(m: => String): Unit = errors.error(m)
   def warning(m: => String): Unit = errors.warning(m)

chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala

@@ -263,6 +263,7 @@ abstract class Definition extends Command {
 case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefDeclass[T <: Data](sourceInfo: SourceInfo, id: T, arg: Arg, lbl: Label) extends Definition
 case class DefEndorse[T <: Data](sourceInfo: SourceInfo, id: T, arg: Arg, lbl: Label) extends Definition
+case class DefNext[T <: Data](sourceInfo: SourceInfo, id: T, arg: Arg) extends Definition
 case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
 case class DefWire(sourceInfo: SourceInfo, id: Data, lbl: Label) extends Definition
 case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg, lbl: Label) extends Definition

coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala

@@ -83,6 +83,14 @@ class EndorseTransform(val c: Context) extends SourceInfoTransformMacro {
   }
 }
 
+class NextTransform(val c: Context) extends SourceInfoTransformMacro {
+  import c.universe._
+  def apply[T: c.WeakTypeTag](arg: c.Tree): c.Tree = {
+    val tpe = weakTypeOf[T]
+    q"$thisObj.do_apply[$tpe]($arg)($implicitSourceInfo)"
+  }
+}
+
 class MuxTransform(val c: Context) extends SourceInfoTransformMacro {
   import c.universe._
   def apply[T: c.WeakTypeTag](cond: c.Tree, con: c.Tree, alt: c.Tree): c.Tree = {

src/main/scala/chisel3/compatibility.scala

@@ -26,6 +26,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val MeetLabelComp = chisel3.core.MeetLabelComp
   val Declassify = chisel3.core.Declassify
   val Endorse = chisel3.core.Endorse
+  val Next = chisel3.core.Next
 
 
   // Not originally part of compatibility.scala

src/main/scala/chisel3/internal/firrtl/Emitter.scala

@@ -32,6 +32,8 @@ private class Emitter(circuit: Circuit, compileTopOnly: Boolean) {
       case e: DefEndorse[_] => 
         val lbl_s = e.lbl.fullName(ctx)
         s"node ${e.name} ${lbl_s} = endorse(${e.arg.fullName(ctx)}, ${lbl_s})"
+      case e: DefNext[_] =>
+        s"node ${e.name} = next(${e.arg.fullName(ctx)})"
       case e: DefWire => s"wire ${e.name} : ${e.lbl.fullName(ctx)}${e.id.toType(ctx)}"
       case e: DefReg => s"reg ${e.name} : ${e.lbl.fullName(ctx)}${e.id.toType(ctx)}, ${e.clock.fullName(ctx)}"
       case e: DefRegInit => s"reg ${e.name} : ${e.lbl.fullName(ctx)}${e.id.toType(ctx)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"

src/main/scala/chisel3/package.scala

@@ -35,6 +35,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   val MeetLabelComp = chisel3.core.MeetLabelComp
   val Declassify = chisel3.core.Declassify
   val Endorse = chisel3.core.Endorse
+  val Next = chisel3.core.Next
 
   // Components
   val C = chisel3.core.C