arch/xtensa/esp32s3: Fix data transmission failure when buffer is in PSRAM #18350
+5
−0
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Summary
PSRAM buffers require explicit cache management when used with DMA, as DMA accesses physical memory directly, bypassing the CPU cache.
Before starting DMA transfer:
cache_writeback_addr()to flush dirty data from cache to PSRAM.cache_invalidate_addr()to invalidate cache lines, ensuring DMA can write to PSRAM.This ensures cache coherence and correct data transmission in burst mode.
Impact
Testing
Environment
Test method
Added temporary debug logs in
esp32s3_spi_dma_exchangeto monitor transfer behavior.Here is the code:
Logs before fix
Logs after fix
Log comparison shows the fix is working:
0xf5 0x00and0xf6 0x00), indicating DMA failed to write data to the buffer (or read from it).defconfig shown below:
defconfig