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arch/arm/stm32h7: fix sdcan clock, ILS register and ID #18300

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Merged
acassis merged 1 commit into from
Feb 10, 2026
+24 −4
Merged

arch/arm/stm32h7: fix sdcan clock, ILS register and ID #18300

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28 changes: 24 additions & 4 deletions arch/arm/src/stm32h7/stm32_fdcan_sock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,10 @@

#define CAN_ERROR_WARNING_THRESHOLD 96

#define WORD_LENGTH 4U

#define CANRAM_WORDS 2560U /* Total words in Message RAM (RM0433) */

/* General Configuration ****************************************************/

#if !defined(CONFIG_SCHED_WORKQUEUE)
Expand Down Expand Up @@ -142,8 +146,11 @@

/* CAN Clock Configuration **************************************************/

#define STM32_FDCANCLK STM32_HSE_FREQUENCY
#ifndef STM32_FDCANCLK
# define STM32_FDCANCLK STM32_HSE_FREQUENCY
#endif
#define CLK_FREQ STM32_FDCANCLK

#define PRESDIV_MAX 256

/* Interrupts ***************************************************************/
Expand Down Expand Up @@ -2046,6 +2053,11 @@ int fdcan_initialize(struct fdcan_driver_s *priv)

if (!g_apb1h_init)
{
/* Clear Message RAM (shared between FDCAN1/2/3) */

memset((void *)STM32_CANRAM_BASE, 0,
CANRAM_WORDS * WORD_LENGTH);

fdcan_apb1hreset();
g_apb1h_init = true;
}
Expand Down Expand Up @@ -2183,7 +2195,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv)

regval = getreg32(priv->base + STM32_FDCAN_ILS_OFFSET);
regval |= FDCAN_ILS_TCL;
putreg32(FDCAN_ILS_TCL, priv->base + STM32_FDCAN_ILS_OFFSET);
putreg32(regval, priv->base + STM32_FDCAN_ILS_OFFSET);

/* Enable Tx buffer transmission interrupts
* Note: Still need fdcan_enable_interrupts() to set ILE (IR line enable)
Expand Down Expand Up @@ -2220,7 +2232,9 @@ int fdcan_initialize(struct fdcan_driver_s *priv)
* and relative address (in words) used for configuration
*/

const uint32_t iface_ram_base = (2560 / 2) * priv->iface_idx;
const uint32_t iface_ram_base =
(CANRAM_WORDS / 2) * priv->iface_idx;

const uint32_t gl_ram_base = STM32_CANRAM_BASE;
uint32_t ram_offset = iface_ram_base;

Expand All @@ -2247,9 +2261,13 @@ int fdcan_initialize(struct fdcan_driver_s *priv)
*
* Discussion:
* https://community.st.com/s/question/0D73W000001nzqFSAQ
*
* vmay23
* Using 64 --> some messages are being received but some are not
* Using 128 --> according to the tests, everything is working fine
*/

const uint8_t n_extid = 64;
const uint8_t n_extid = 128;
priv->message_ram.filt_extid_addr = gl_ram_base + ram_offset * WORD_LENGTH;

regval = (n_extid << FDCAN_XIDFC_LSE_SHIFT) & FDCAN_XIDFC_LSE_MASK;
Expand Down Expand Up @@ -2284,7 +2302,9 @@ int fdcan_initialize(struct fdcan_driver_s *priv)

regval = (ram_offset << FDCAN_RXF0C_F0SA_SHIFT) & FDCAN_RXF0C_F0SA_MASK;
regval |= (NUM_RX_FIFO0 << FDCAN_RXF0C_F0S_SHIFT) & FDCAN_RXF0C_F0S_MASK;

putreg32(regval, priv->base + STM32_FDCAN_RXF0C_OFFSET);

ram_offset += NUM_RX_FIFO0 * FIFO_ELEMENT_SIZE;

/* Not using Rx FIFO1 */
Expand Down
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