stm32h7/clk: work in progress

arch/arm/src/armv7-m/CMakeLists.txt

@@ -34,7 +34,6 @@ set(SRCS
     arm_initialstate.c
     arm_itm.c
     arm_memfault.c
-    arm_perf.c
     arm_schedulesigaction.c
     arm_sigdeliver.c
     arm_svcall.c
@@ -45,6 +44,11 @@ set(SRCS
     arm_vectors.c
     arm_dbgmonitor.c)
 
+
+if(CONFIG_ARCH_HAVE_PERF_EVENTS)
+  arm_perf.c
+endif()
+
 if(CONFIG_ARMV7M_SYSTICK)
   list(APPEND SRCS arm_systick.c)
 endif()

arch/arm/src/armv7-m/Make.defs

@@ -28,7 +28,7 @@ CMN_ASRCS += arm_exception.S arm_saveusercontext.S
 
 CMN_CSRCS += arm_busfault.c arm_cache.c arm_cpuinfo.c arm_doirq.c
 CMN_CSRCS += arm_hardfault.c arm_initialstate.c arm_itm.c
-CMN_CSRCS += arm_memfault.c arm_perf.c
+CMN_CSRCS += arm_memfault.c 
 CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
 CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_tcbinfo.c
 CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_dbgmonitor.c
@@ -37,6 +37,10 @@ ifneq ($(CONFIG_ARCH_HAVE_CUSTOM_VECTORS),y)
   CMN_CSRCS += arm_vectors.c
 endif
 
+ifeq ($(CONFIG_ARCH_HAVE_PERF_EVENTS),y)
+  CMN_CSRDS += arm_perf.c
+endif
+
 ifeq ($(CONFIG_ARMV7M_SYSTICK),y)
   CMN_CSRCS += arm_systick.c
 endif

arch/arm/src/armv7-m/arm_perf.c

@@ -32,8 +32,6 @@
 #include "itm.h"
 #include "nvic.h"
 
-#ifdef CONFIG_ARCH_HAVE_PERF_EVENTS
-
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -78,4 +76,3 @@ void up_perf_convert(clock_t elapsed, struct timespec *ts)
   left        = elapsed - ts->tv_sec * g_cpu_freq;
   ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_cpu_freq;
 }
-#endif

arch/arm/src/stm32h7/CMakeLists.txt

@@ -30,11 +30,14 @@ list(
   stm32_gpio.c
   stm32_irq.c
   stm32_start.c
-  stm32_rcc.c
   stm32_lowputc.c
   stm32_serial.c
   stm32_uid.c)
 
+if(CONFIG_CLK)
+  list(APPEND SRCS stm32_clk.c)
+endif()
+
 if(CONFIG_STM32H7_PROGMEM)
   list(APPEND SRCS stm32_flash.c)
 endif()

arch/arm/src/stm32h7/Make.defs

@@ -46,9 +46,13 @@ endif
 # Required STM32H7 files
 
 CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c
-CHIP_CSRCS += stm32_start.c stm32_rcc.c stm32_lowputc.c stm32_serial.c
+CHIP_CSRCS += stm32_start.c stm32_serial.c
 CHIP_CSRCS += stm32_uid.c
 
+ifeq ($(CONFIG_CLK),y)
+CHIP_CSRCS += stm32_clk.c
+endif
+
 ifeq ($(CONFIG_SCHED_TICKLESS),y)
 CHIP_CSRCS += stm32_tickless.c
 else

arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h

@@ -431,6 +431,17 @@
 
 /* Bit definitions for RCC_PLL1DIVR register */
 
+#define RCC_PLLDIVR_N_SHIFT           (0ul)
+#define RCC_PLLDIVR_N(x)              (((x) - 1) << RCC_PLL1DIVR_N_SHIFT)  /* Multiplication factor for VCO: 4 - 512 */
+#define RCC_PLLDIVR_P_SHIFT           (9ul)
+#define RCC_PLLDIVR_P(x)              (((x) - 1) << RCC_PLL1DIVR_P_SHIFT)  /* DIVP division factor: 2 - 128, must be even */
+#define RCC_PLLDIVR_Q_SHIFT           (16ul)
+#define RCC_PLLDIVR_Q(x)              (((x) - 1) << RCC_PLL1DIVR_Q_SHIFT)  /* DIVQ division factor: 2 - 128 */
+#define RCC_PLLDIVR_R_SHIFT           (24ul)
+#define RCC_PLLDIVR_R(x)              (((x) - 1) << RCC_PLL1DIVR_R_SHIFT)  /* DIVR division factor: 2 - 128 */
+
+/* Bit definitions for RCC_PLL1DIVR register */
+
 #define RCC_PLL1DIVR_N1_SHIFT           (0ul)
 #define RCC_PLL1DIVR_N1(x)              (((x) - 1) << RCC_PLL1DIVR_N1_SHIFT)  /* Multiplication factor for VCO: 4 - 512 */
 #define RCC_PLL1DIVR_P1_SHIFT           (9ul)