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STM32F7 I2S Support #3362

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STM32F7 I2S Support #3362

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701e1ed
hw/mcu/stm32f7: Add I2SPLL configuration
kasjer Jan 14, 2025
39ef94e
hw/drivers/i2s: Add I2S driver for STM32F7 family
kasjer Jan 15, 2025
c29eaf0
bsp/nucleo-f7xx: Add configuration for I2S
kasjer Jan 15, 2025
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2 changes: 1 addition & 1 deletion hw/bsp/nucleo-f746zg/include/bsp/stm32f7xx_hal_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,6 @@
#define HAL_NOR_MODULE_ENABLED
#define HAL_SDRAM_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_DFSDM_MODULE_ENABLED
Expand All @@ -87,6 +86,7 @@
#define HAL_SRAM_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LPTIM_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
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11 changes: 11 additions & 0 deletions hw/bsp/nucleo-f746zg/syscfg.yml
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Expand Up @@ -37,10 +37,21 @@ syscfg.vals:
STM32_CLOCK_HSI: 0
STM32_CLOCK_HSE: 1
STM32_CLOCK_HSE_BYPASS: 1
# Input clock for all PLLs 8MHz / 8 = 1 MHz
STM32_CLOCK_PLL_PLLM: 8
# VCO = 1MHz * 432 = 432 MHz
STM32_CLOCK_PLL_PLLN: 432
# PLLP - PLLCLK = VCO / 2 = 216
STM32_CLOCK_PLL_PLLP: 2
# PLLQ - PLL48CLK = VCO / 9 = 48
STM32_CLOCK_PLL_PLLQ: 9
STM32_CLOCK_PLLI2S_PLLN: 384
# PLLI2SP - SPDIFRX = 48 MHz
STM32_CLOCK_PLLI2S_PLLP: 8
# PLLI2SQ - SAICLK = 192 MHz
STM32_CLOCK_PLLI2S_PLLQ: 2
# PLLI2SR - I2SCLK = 192 MHz
STM32_CLOCK_PLLI2S_PLLR: 2
STM32_CLOCK_ENABLE_OVERDRIVE: 0
STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV4'
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2 changes: 1 addition & 1 deletion hw/bsp/nucleo-f767zi/include/bsp/stm32f7xx_hal_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,6 @@
#define HAL_NOR_MODULE_ENABLED
#define HAL_SDRAM_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_DFSDM_MODULE_ENABLED
#define HAL_DSI_MODULE_ENABLED
#define HAL_JPEG_MODULE_ENABLED
Expand All @@ -85,6 +84,7 @@
#define HAL_SRAM_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LPTIM_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
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12 changes: 12 additions & 0 deletions hw/bsp/nucleo-f767zi/syscfg.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -37,11 +37,23 @@ syscfg.vals:
STM32_CLOCK_HSI: 0
STM32_CLOCK_HSE: 1
STM32_CLOCK_HSE_BYPASS: 1
# Input clock for all PLLs 8MHz / 8 = 1 MHz
STM32_CLOCK_PLL_PLLM: 8
# VCO = 1MHz * 432 = 432 MHz
STM32_CLOCK_PLL_PLLN: 432
# PLLP - PLLCLK = VCO / 2 = 216
STM32_CLOCK_PLL_PLLP: 2
# PLLQ - PLL48CLK = VCO / 9 = 48
STM32_CLOCK_PLL_PLLQ: 9
# PLLR - PLLDSICLK = VCO / 7 = 30.85 MHz
STM32_CLOCK_PLL_PLLR: 7
STM32_CLOCK_PLLI2S_PLLN: 384
# PLLI2SP - SPDIFRX = 48 MHz
STM32_CLOCK_PLLI2S_PLLP: 8
# PLLI2SQ - SAICLK = 192 MHz
STM32_CLOCK_PLLI2S_PLLQ: 2
# PLLI2SR - I2SCLK = 192 MHz
STM32_CLOCK_PLLI2S_PLLR: 2
STM32_CLOCK_ENABLE_OVERDRIVE: 0
STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV4'
Expand Down
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