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Fix Rustdocs (amd64, nightly)" CI check #5727

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Merged
merged 2 commits into from
May 7, 2024
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Fix Rustdocs (amd64, nightly)" CI check #5727

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e457ff5
Remove unknown targets
alamb May 6, 2024
d27a92c
Fix parquet format lint
alamb May 6, 2024
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12 changes: 0 additions & 12 deletions arrow-buffer/src/alloc/alignment.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -80,15 +80,6 @@ pub const ALIGNMENT: usize = 1 << 5;
#[cfg(target_arch = "sparc64")]
pub const ALIGNMENT: usize = 1 << 6;

// On ARM cache line sizes are fixed. both v6 and v7.
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This is removed because these target_arch apparently do not exist

warning: unexpected `cfg` condition value: `thumbv7`
  --> arrow-buffer/src/alloc/alignment.rs:89:7
   |
89 | #[cfg(target_arch = "thumbv7")]
   |       ^^^^^^^^^^^^^^^^^^^^^^^
   |
   = note: expected values for `target_arch` are: `aarch64`, `arm`, `arm64ec`, `avr`, `bpf`, `csky`, `hexagon`, `loongarch64`, `m68k`, `mips`, `mips32r6`, `mips64`, `mips64r6`, `msp430`, `nvptx64`, `powerpc`, `powerpc64`, `riscv32`, `riscv64`, `s390x`, `sparc`, `sparc64`, `wasm32`, `wasm64`, `x86`, `x86_64`
   = note: see <https://doc.rust-lang.org/nightly/cargo/reference/build-scripts.html#rustc-check-cfg> for more information about checking conditional configuration

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This is interesting. I tried searching up to understand more but can't really find much to point towards existence of those target_arch values, even though targets like thumbv6m-none-eabi exist

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I think this file is very old ( so it may be something lost to the mists of time ) --

According to some archeology on 1be5358 it looks like it was introduced in apache/arrow#9495 when this file was still part of the arrow mono repo and @jorgecarleitao was working on arrow2

// Need to add board specific or platform specific things later.
/// Cache and allocation multiple alignment size
#[cfg(target_arch = "thumbv6")]
pub const ALIGNMENT: usize = 1 << 5;
/// Cache and allocation multiple alignment size
#[cfg(target_arch = "thumbv7")]
pub const ALIGNMENT: usize = 1 << 5;

// Operating Systems cache size determines this.
// Currently no way to determine this without runtime inference.
/// Cache and allocation multiple alignment size
Expand All @@ -107,9 +98,6 @@ pub const ALIGNMENT: usize = 1 << 5;
// If you have smaller data with less padded functionality then use 32 with force option.
// - https://devtalk.nvidia.com/default/topic/803600/variable-cache-line-width-/
/// Cache and allocation multiple alignment size
#[cfg(target_arch = "nvptx")]
pub const ALIGNMENT: usize = 1 << 7;
/// Cache and allocation multiple alignment size
#[cfg(target_arch = "nvptx64")]
pub const ALIGNMENT: usize = 1 << 7;

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3 changes: 2 additions & 1 deletion parquet/src/format.rs
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2 changes: 2 additions & 0 deletions parquet/src/lib.rs
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Expand Up @@ -107,6 +107,8 @@ pub mod basic;
/// Automatically generated code for reading parquet thrift definition.
// see parquet/CONTRIBUTING.md for instructions on regenerating
#[allow(clippy::derivable_impls, clippy::match_single_binding)]
// Don't try and format auto generated code
#[rustfmt::skip]
pub mod format;

#[macro_use]
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