Support multidimensional ports - #18
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tmichalak
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Aug 13, 2026
tmichalak
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Aug 13, 2026
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@mohamed Please fix the issues pointed out by the linter |
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I think it would be a good idea to add tests for arrays with more than two dimensions. I also think a test going from a design YAML with a multidimensional port to a SystemVerilog module would be good to have, to make sure we generate the correct syntax etc. |
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@tmichalak @kslominski-ant The branch has been updated. Please have a look and let me know if you have further comments |
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Please update the documentation. Apart from this squash the commits and rebase your branch. |
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@tmichalak Documentation has been updated. Please have a look and let me know if there are further changes needed. |
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@tmichalak @kslominski-ant I have squashed the commits and rebased the branch. |
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Add support for multidimensional design and IP ports. This is achieved by using the `bound` property to specify the port dimensions. Signed-off-by: Mohamed A. Bamakhrama <mohamed.bamakhrama@imec-int.com>
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Add support for multidimensional design and IP ports.
This is achieved by using the
boundproperty to specify the port dimensions.