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Merge tag 'AU_LINUX_ANDROID_LA.BF.2.1_RB1.05.00.00.173.031' into andr…
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…oid-3.10-dev

AU_LINUX_ANDROID_LA.BF.2.1_RB1.05.00.00.173.031 based on quic/aosp/LA.BF.2.1_rb1

Change-Id: Id6bc6f8065a224c5bd6146a99633bdc0e7ff1f34
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@erikcas
erikcas committed Feb 19, 2015
2 parents e776111 + d6a4e4e commit d820e62
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Showing 48 changed files with 1,179 additions and 571 deletions.
4 changes: 2 additions & 2 deletions arch/arm/boot/dts/qcom/apq8084-mdss.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -144,6 +144,7 @@
mdss_fb1: qcom,mdss_fb_external {
cell-index = <1>;
compatible = "qcom,mdss-fb";
qcom,memblock-reserve = <0x05200000 0x01E00000>;
};

mdss_fb2: qcom,mdss_fb_wfd {
Expand Down Expand Up @@ -332,9 +333,8 @@
cell-index = <0>;
compatible = "qcom,hdmi-tx";
reg = <0xfd922100 0x380>,
<0xfd922500 0x7C>,
<0xfc4b8000 0x6100>;
reg-names = "core_physical", "phy_physical", "qfprom_physical";
reg-names = "core_physical", "qfprom_physical";

hpd-gdsc-supply = <&gdsc_mdss>;
hpd-5v-supply = <&pma8084_mvs1>;
Expand Down
1 change: 1 addition & 0 deletions arch/arm/configs/apq8084-perf_defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -188,6 +188,7 @@ CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
CONFIG_NETFILTER_XT_MATCH_ESP=y
CONFIG_NF_CONNTRACK_IPV4=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=y
Expand Down
1 change: 1 addition & 0 deletions arch/arm/configs/apq8084_defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -190,6 +190,7 @@ CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
CONFIG_NETFILTER_XT_MATCH_ESP=y
CONFIG_NF_CONNTRACK_IPV4=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=y
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/mach-msm/board-8084-gpiomux.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1278,7 +1278,7 @@ void __init apq8084_init_gpiomux(void)
} else {
msm_gpiomux_install(apq8084_hsic_configs,
ARRAY_SIZE(apq8084_hsic_configs));
msm_gpiomux_install(msm_hdmi_configs,
msm_gpiomux_install_nowrite(msm_hdmi_configs,
ARRAY_SIZE(msm_hdmi_configs));
msm_gpiomux_install(hap_lvl_shft_config,
ARRAY_SIZE(hap_lvl_shft_config));
Expand All @@ -1292,7 +1292,7 @@ void __init apq8084_init_gpiomux(void)
msm_gpiomux_install(msm_sbc_sensor_configs,
ARRAY_SIZE(msm_sbc_sensor_configs));
else
msm_gpiomux_install(msm_sensor_configs,
msm_gpiomux_install_nowrite(msm_sensor_configs,
ARRAY_SIZE(msm_sensor_configs));
msm_gpiomux_install(msm_pcie_configs, ARRAY_SIZE(msm_pcie_configs));
msm_gpiomux_install(msm_epm_configs, ARRAY_SIZE(msm_epm_configs));
Expand Down
131 changes: 110 additions & 21 deletions arch/arm/mach-msm/clock-mdss-8974.c
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Original file line number Diff line number Diff line change
Expand Up @@ -216,6 +216,8 @@ static void hdmi_vco_disable(struct clk *c)
REG_W(0x0, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(5);
REG_W(0x0, hdmi_phy_base + HDMI_PHY_GLB_CFG);
udelay(5);
REG_W(0x7F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);

clk_disable(mdss_ahb_clk);

Expand Down Expand Up @@ -253,7 +255,7 @@ static int hdmi_vco_enable(struct clk *c)
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(350);

/* PLL Power-Up */
/* PLL Power-Up */
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(350);

Expand Down Expand Up @@ -479,9 +481,20 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0xF4, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x02, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(200);

REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x07, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
Expand Down Expand Up @@ -523,9 +536,20 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0x2a, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0X1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(200);

REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x07, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);

REG_W(0X0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0XDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
Expand Down Expand Up @@ -567,9 +591,20 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0x2A, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(200);

REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x07, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
Expand Down Expand Up @@ -609,9 +644,20 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0x8A, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x02, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(200);

REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x07, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
Expand Down Expand Up @@ -655,9 +701,20 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0xE6, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x02, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(200);

REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x07, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
Expand Down Expand Up @@ -698,9 +755,20 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0x38, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(200);

REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x07, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
Expand Down Expand Up @@ -741,9 +809,19 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0x3E, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);

REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x07, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
Expand Down Expand Up @@ -784,9 +862,20 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0xCD, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(200);

REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x07, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
Expand All @@ -798,7 +887,7 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x3F, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
udelay(200);
break;
Expand All @@ -812,7 +901,15 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);

REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x07, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
Expand All @@ -838,18 +935,9 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
if (rate < 825000000)
REG_W(0x01, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
else
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x3F, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);

REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
REG_W(0x62, hdmi_phy_base + HDMI_PHY_BIST_PATN0);
REG_W(0x03, hdmi_phy_base + HDMI_PHY_BIST_PATN1);
REG_W(0x69, hdmi_phy_base + HDMI_PHY_BIST_PATN2);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_BIST_PATN3);

udelay(200);

REG_W(0x00, hdmi_phy_base + HDMI_PHY_BIST_CFG1);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_BIST_CFG0);
}

/* Make sure writes complete before disabling iface clock */
Expand Down Expand Up @@ -2810,6 +2898,7 @@ static struct clk_ops hdmi_mux_ops;
static int hdmi_mux_prepare(struct clk *c)
{
int ret = 0;
ret = clk_prepare(mdss_ahb_clk);

if (c && c->ops && c->ops->set_rate)
ret = c->ops->set_rate(c, c->rate);
Expand Down
39 changes: 0 additions & 39 deletions arch/arm/mach-msm/include/mach/msm_hdmi_audio_codec.h
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