ADRV9026/ZCU102: Upgrade DMA

[AndrDragomir]

PR Description

Increase DMA clock to 333MHz to improve performance
This PR fixes a data integrity issue on the no-OS version of the JESD204C use case
Fix JESD block diagrams in the documentation

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)
• Documentation

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[StancaPop]

In the above diagrams, RX DMA data output width has been modified from 64b to 128b. Is this only for the ZCU102 case, or also for the VCU118?

[AndrDragomir]

It's for both ZCU102 and VCU118.