JESD204C: Add FEC and pipeline stages

library/common/ad_mem_dist.v

@@ -0,0 +1,73 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_mem_dist #(
+  parameter RAM_WIDTH = 32,
+  parameter RAM_ADDR_BITS = 4,
+  parameter REGISTERED_OUTPUT = 1
+)(
+  output wire  [RAM_WIDTH-1:0]      rd_data,
+  input  wire                       clk,
+  input  wire                       wr_en,
+  input  wire  [RAM_ADDR_BITS-1:0]  wr_addr,
+  input  wire  [RAM_WIDTH-1:0]      wr_data,
+  input  wire  [RAM_ADDR_BITS-1:0]  rd_addr
+);
+
+  (* ram_style="distributed" *)
+  reg [RAM_WIDTH-1:0] ram [(2**RAM_ADDR_BITS)-1:0];
+
+  reg [RAM_WIDTH-1:0] rd_data_s;
+
+  always @(posedge clk)
+    if (wr_en)
+      ram[wr_addr] <= wr_data;
+
+  generate if (REGISTERED_OUTPUT) begin
+    always @(posedge clk) begin
+      rd_data_s <= ram[rd_addr];
+    end
+  end else begin
+    always @(*) begin
+      rd_data_s = ram[rd_addr];
+    end
+  end
+  endgenerate
+
+  assign rd_data = rd_data_s;
+
+endmodule

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -52,7 +52,8 @@ module ad_ip_jesd204_tpl_adc #(
   parameter TWOS_COMPLEMENT = 1,
   parameter EXT_SYNC = 0,
   parameter PN7_ENABLE = 1,
-  parameter PN15_ENABLE = 1
+  parameter PN15_ENABLE = 1,
+  parameter NUM_PIPELINE_STAGES = 0
 ) (
 
   // jesd interface
@@ -209,7 +210,8 @@ module ad_ip_jesd204_tpl_adc #(
     .DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
     .EXT_SYNC (EXT_SYNC),
     .PN7_ENABLE (PN7_ENABLE),
-    .PN15_ENABLE(PN15_ENABLE)
+    .PN15_ENABLE(PN15_ENABLE),
+    .NUM_PIPELINE_STAGES (NUM_PIPELINE_STAGES)
   ) i_core (
     .clk (link_clk),
 

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -50,7 +50,8 @@ module ad_ip_jesd204_tpl_adc_core #(
   parameter TWOS_COMPLEMENT = 1,
   parameter EXT_SYNC = 0,
   parameter PN7_ENABLE = 1,
-  parameter PN15_ENABLE = 1
+  parameter PN15_ENABLE = 1,
+  parameter NUM_PIPELINE_STAGES = 0
 ) (
   input clk,
 
@@ -119,7 +120,8 @@ module ad_ip_jesd204_tpl_adc_core #(
     .OCTETS_PER_BEAT (OCTETS_PER_BEAT),
     .EN_FRAME_ALIGN (EN_FRAME_ALIGN),
     .LINK_DATA_WIDTH (LINK_DATA_WIDTH),
-    .ADC_DATA_WIDTH (ADC_DATA_WIDTH)
+    .ADC_DATA_WIDTH (ADC_DATA_WIDTH),
+    .NUM_PIPELINE_STAGES (NUM_PIPELINE_STAGES)
   ) i_deframer (
     .clk (clk),
     .link_sof (link_sof),

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -43,6 +43,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
   parameter SAMPLES_PER_FRAME = 1,
   parameter OCTETS_PER_BEAT = 8,
   parameter EN_FRAME_ALIGN = 0,
+  parameter NUM_PIPELINE_STAGES = 0,
   parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
   parameter ADC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
 ) (
@@ -65,19 +66,39 @@ module ad_ip_jesd204_tpl_adc_deframer #(
                                        NUM_CHANNELS / NUM_LANES;
   localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME;
 
+  wire [LINK_DATA_WIDTH-1:0] link_data_r;
+  wire [LINK_DATA_WIDTH-1:0] frame_data_r;
+  wire [LINK_DATA_WIDTH-1:0] adc_data_r;
+
   wire [LINK_DATA_WIDTH-1:0] link_data_s;
   wire [LINK_DATA_WIDTH-1:0] link_data_msb_s;
   wire [LINK_DATA_WIDTH-1:0] frame_data_s;
   wire [LINK_DATA_WIDTH-1:0] adc_data_msb;
 
+  util_pipeline_stage #(
+    .REGISTERED (NUM_PIPELINE_STAGES),
+    .WIDTH (3*LINK_DATA_WIDTH)
+  ) i_pipeline_stages (
+    .clk (clk),
+    .in ({
+      link_data_s,
+      frame_data_s,
+      adc_data_msb
+    }),
+    .out ({
+      link_data_r,
+      frame_data_r,
+      adc_data_r
+    }));
+
   // data multiplex
 
   genvar i;
   genvar j;
   generate
     /* Reorder octets MSB first */
     for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_adc_data
-      assign link_data_msb_s[i+:8] = link_data_s[LINK_DATA_WIDTH-1-i-:8];
+      assign link_data_msb_s[i+:8] = link_data_r[LINK_DATA_WIDTH-1-i-:8];
     end
 
     /* Slice lanes into frames */
@@ -95,7 +116,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
       .WORDS_PER_GROUP (NUM_CHANNELS),
       .WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME)
     ) i_frames_to_channels (
-      .data_in (frame_data_s),
+      .data_in (frame_data_r),
       .data_out (adc_data_msb));
 
     /* Reorder samples LSB first and remove tail bits */
@@ -105,7 +126,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
       localparam src_msb = LINK_DATA_WIDTH - 1 - i * src_w ;
       localparam dst_lsb = i * dst_w;
 
-      assign adc_data[dst_lsb+:dst_w] = adc_data_msb[src_msb-:dst_w];
+      assign adc_data[dst_lsb+:dst_w] = adc_data_r[src_msb-:dst_w];
     end
   endgenerate
 

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2018-2022, 2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2018-2022, 2024-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIJESD204
 ###############################################################################
 
@@ -50,6 +50,12 @@ ad_ip_parameter OCTETS_PER_BEAT INTEGER 4 true [list \
   GROUP $group \
 ]
 
+ad_ip_parameter NUM_PIPELINE_STAGES INTEGER 0 true [list \
+  DISPLAY_NAME "Number of pipeline stages inside the deframer" \
+  ALLOWED_RANGES {0 1 2} \
+  GROUP $group \
+]
+
 set group "JESD204 Deframer Configuration"
 
 ad_ip_parameter NUM_LANES INTEGER 1 true [list \

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2018-2022, 2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIJESD204
 ###############################################################################
 
@@ -21,6 +21,7 @@ adi_ip_files ad_ip_jesd204_tpl_adc [list \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
   "$ad_hdl_dir/library/common/util_ext_sync.v" \
   "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
+  "$ad_hdl_dir/library/common/util_pipeline_stage.v" \
   "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
   "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
   "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
@@ -68,6 +69,7 @@ foreach {p v} {
   "CONVERTER_RESOLUTION" "8 11 12 14 16" \
   "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
   "OCTETS_PER_BEAT" "4 6 8 12 16 32 64" \
+  "NUM_PIPELINE_STAGES" "0 1 2" \
 } { \
   set_property -dict [list \
     "value_validation_type" "list" \

library/jesd204/axi_jesd204_common/jesd204_up_common.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2016-2022, 2025 Analog Devices, Inc. All rights reserved.
 // SPDX short identifier: ADIJESD204
 // ***************************************************************************
 // ***************************************************************************
@@ -54,6 +54,7 @@ module jesd204_up_common #(
   output reg [7:0] core_cfg_octets_per_frame = 'h00,
   output reg core_cfg_disable_scrambler = 'h00,
   output reg core_cfg_disable_char_replacement = 'h00,
+  output reg [1:0] core_cfg_header_mode = 'h00,
   output reg [EXTRA_CFG_WIDTH-1:0] core_extra_cfg = 'h00,
 
   output reg [DEV_EXTRA_CFG_WIDTH-1:0] device_extra_cfg = 'h00,
@@ -75,6 +76,7 @@ module jesd204_up_common #(
   reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}};
   reg [NUM_LINKS-1:0] up_cfg_links_disable = {NUM_LINKS{1'b0}};
   reg up_cfg_disable_char_replacement = 1'b0;
+  reg [1:0] up_cfg_header_mode = 1'b0;
   reg up_cfg_disable_scrambler = 1'b0;
 
   /* Reset for the register map */
@@ -164,6 +166,7 @@ module jesd204_up_common #(
       core_cfg_links_disable <= up_cfg_links_disable;
       core_cfg_disable_scrambler <= up_cfg_disable_scrambler;
       core_cfg_disable_char_replacement <= up_cfg_disable_char_replacement;
+      core_cfg_header_mode <= up_cfg_header_mode;
       core_extra_cfg <= up_extra_cfg;
     end
   end
@@ -291,7 +294,8 @@ module jesd204_up_common #(
         /* 00-09 */ up_cfg_octets_per_multiframe
       };
       12'h85: up_rdata = {
-        /* 02-31 */ 30'h00, /* Reserved for future additions */
+        /* 04-31 */ 30'h00, /* Reserved for future additions */
+        /* 03-02 */ up_cfg_header_mode, /* 0 - CRC12 ; 1 - CRC3; 2 - FEC; 3 - CMD */
         /*    01 */ up_cfg_disable_char_replacement, /* Disable character replacement */
         /*    00 */ up_cfg_disable_scrambler /* Disable scrambler */
       };
@@ -335,6 +339,7 @@ module jesd204_up_common #(
       up_cfg_beats_per_multiframe <= 'h00;
 
       up_cfg_disable_char_replacement <= 1'b0;
+      up_cfg_header_mode <= 2'b0;
       up_cfg_disable_scrambler <= 1'b0;
     end else if (up_wreq == 1'b1) begin
       case (up_waddr)
@@ -364,6 +369,7 @@ module jesd204_up_common #(
                                             {DATA_PATH_WIDTH_LOG2{1'b1}}};
           end
           12'h085: begin
+            up_cfg_header_mode <= up_wdata[3:2];
             up_cfg_disable_char_replacement <= up_wdata[1];
             up_cfg_disable_scrambler <= up_wdata[0];
           end

library/jesd204/axi_jesd204_common/jesd204_up_sysref.v

@@ -1,13 +1,15 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2016-2018, 2020-2022, 2025 Analog Devices, Inc. All rights reserved.
 // SPDX short identifier: ADIJESD204
 // ***************************************************************************
 // ***************************************************************************
 
 `timescale 1ns/100ps
 
-module jesd204_up_sysref (
+module jesd204_up_sysref #(
+  parameter DATA_PATH_WIDTH_LOG2 = 0
+) (
   input up_clk,
   input up_reset,
 
@@ -90,7 +92,7 @@ module jesd204_up_sysref (
         end
         12'h041: begin
           /* Must be aligned to data path width */
-          up_cfg_lmfc_offset <= up_wdata;
+          up_cfg_lmfc_offset <= up_wdata[9:DATA_PATH_WIDTH_LOG2];
         end
       endcase
     end

library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2016-2022, 2025 Analog Devices, Inc. All rights reserved.
 // SPDX short identifier: ADIJESD204
 // ***************************************************************************
 // ***************************************************************************
@@ -53,6 +53,7 @@ module axi_jesd204_rx #(
   output [7:0] core_cfg_octets_per_frame,
   output core_cfg_disable_scrambler,
   output core_cfg_disable_char_replacement,
+  output [1:0] core_cfg_header_mode,
   output [7:0] core_cfg_frame_align_err_threshold,
 
   output [9:0] device_cfg_octets_per_multiframe,
@@ -73,7 +74,7 @@ module axi_jesd204_rx #(
   input core_event_frame_alignment_error,
   input core_event_unexpected_lane_state_error,
 
-  output [6:0] core_ctrl_err_statistics_mask,
+  output [8:0] core_ctrl_err_statistics_mask,
   output core_ctrl_err_statistics_reset,
 
   input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
@@ -90,9 +91,11 @@ module axi_jesd204_rx #(
   input [31:0] status_synth_params2
 );
 
-  localparam PCORE_VERSION = 32'h00010761; // 1.07.a
+  localparam PCORE_VERSION = 32'h00010861; // 1.08.a
   localparam PCORE_MAGIC = 32'h32303452; // 204R
 
+  localparam DATA_PATH_WIDTH_LOG2 = (DATA_PATH_WIDTH == 8) ? 3 : 2;
+
   /* Register interface signals */
   reg [31:0] up_rdata = 'h0;
   reg up_wack = 1'b0;
@@ -209,6 +212,7 @@ module axi_jesd204_rx #(
     .core_cfg_links_disable(core_cfg_links_disable),
     .core_cfg_disable_scrambler(core_cfg_disable_scrambler),
     .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
+    .core_cfg_header_mode(core_cfg_header_mode),
 
     .up_extra_cfg({
       /* 00-07 */ up_cfg_frame_align_err_threshold
@@ -240,7 +244,9 @@ module axi_jesd204_rx #(
     .status_synth_params1(status_synth_params1),
     .status_synth_params2(status_synth_params2));
 
-  jesd204_up_sysref i_up_sysref (
+  jesd204_up_sysref #(
+    .DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
+  ) i_up_sysref (
     .up_clk(s_axi_aclk),
     .up_reset(up_reset),
 
@@ -263,7 +269,8 @@ module axi_jesd204_rx #(
 
   jesd204_up_rx #(
     .NUM_LANES(NUM_LANES),
-    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
+    .DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
   ) i_up_rx (
     .up_clk(s_axi_aclk),
     .up_reset(up_reset),