ad_gmsl2eth_sl: Add voltage levels in READMEs

[StancaPop]

PR Description

Add voltage levels & flags in ad_gmsl2eth_sl README files.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)
• Documentation

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[IuliaCMoldovan]

Tagging @alin724 just to make sure

[alin724]

The VADJ notion won't be applicable here, as we don't have a FMC connector on this evaluation kit (is an evaluation kit made around K26 SoM [Zynq Ultrascale+ FPGA + ZynqMPSoC] but won't have FMC connectors that are connected to different IC's evaluation kits). We can mention the voltage level for the D-PHY-related I/Os that are then connected to the GMSL deserializer's pins, and for the I/O header's pins (a list-based element in the doc)

Needs update.

[IuliaCMoldovan]

Should be merged before #1883