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axi_dmac: Fix AXI transfers of one beat length #1844

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axi_dmac: Fix AXI transfers of one beat length #1844

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@podgori podgori commented Jul 21, 2025

This commit fixes the AXI transfers on both source and destination interfaces which have the length of one beat per burst/packet.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@podgori
axi_dmac: Fix AXI transfers of one beat length
093b1e5 
This commit fixes the AXI transfers on both source and destination
interfaces which have the length of one beat per burst/packet.

Signed-off-by: Ionut Podgoreanu <[email protected]>
@podgori podgori added the bug label Jul 21, 2025
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