Add optional generic pipeline stage in util_do_ram

[podgori]

This commit makes the pipeline_stage module generic so that it can be imported by the util_do_ram to address timing issues in projects.
Two extra parameters are added in util_do_ram to control the pipeline length and the Read FIFO depth to ensure continuous data transmission.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[IuliaCMoldovan]

Suggested change

	.in({
	rd_valid_l1,
	rd_last_l1,
	rd_data,
	rd_keep
	}),
	.out({
	rd_valid_s,
	rd_last_s,
	rd_data_s,
	rd_keep_s
	}));
	.in({
	rd_valid_l1,
	rd_last_l1,
	rd_data,
	rd_keep}),
	.out({
	rd_valid_s,
	rd_last_s,
	rd_data_s,
	rd_keep_s}));