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Feb 28, 2024
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1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -108,3 +108,4 @@ _build
.github/CODEOWNERS
.github/PULL_REQUEST_TEMPLATE.md
library/**/.lock
library/**/interfaces/*.sv
2 changes: 1 addition & 1 deletion docs/library/spi_engine/spi-bus-interface.rst
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ Files

* - Name
- Description
* - :git-hdl:`library/spi_engine/interfaces/spi_master_rtl.xml`
* - :git-hdl:`library/spi_engine/interfaces/spi_engine_rtl.xml`
- Interface definition file

Signal Pins
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4 changes: 3 additions & 1 deletion library/axi_ad5766/Makefile
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
Expand All @@ -25,4 +25,6 @@ XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml

XILINX_LIB_DEPS += util_cdc

XILINX_INTERFACE_DEPS += spi_engine/interfaces

include ../scripts/library.mk
1 change: 1 addition & 0 deletions library/interfaces/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ M_VIVADO := vivado -mode batch -source

M_FLIST := *.log
M_FLIST += *.jou
M_FLIST += *.sv
M_FLIST += if_xcvr_cm.xml
M_FLIST += if_xcvr_cm_rtl.xml
M_FLIST += if_xcvr_ch.xml
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1 change: 1 addition & 0 deletions library/jesd204/interfaces/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@ XML_FLIST += jesd204_rx_event_rtl.xml

M_FLIST := *.log
M_FLIST += *.jou
M_FLIST += *.sv
M_FLIST += $(XML_FLIST)

.PHONY: all xilinx clean clean-all
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4 changes: 3 additions & 1 deletion library/spi_engine/axi_spi_engine/Makefile
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
Expand All @@ -22,6 +22,8 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_cdc

XILINX_INTERFACE_DEPS += spi_engine/interfaces

INTEL_DEPS += ../../common/ad_mem.v
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
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47 changes: 23 additions & 24 deletions library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -34,37 +34,36 @@ adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd_data" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync_data" "SYNC_DATA"} \
{"cmd_ready" "cmd_ready"} \
{"cmd_valid" "cmd_valid"} \
{"cmd_data" "cmd_data"} \
{"sdo_data_ready" "sdo_ready"} \
{"sdo_data_valid" "sdo_valid"} \
{"sdo_data" "sdo_data"} \
{"sdi_data_ready" "sdi_ready"} \
{"sdi_data_valid" "sdi_valid"} \
{"sdi_data" "sdi_data"} \
{"sync_ready" "sync_ready"} \
{"sync_valid" "sync_valid"} \
{"sync_data" "sync_data"} \
}
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master"

adi_add_bus "spi_engine_offload_ctrl0" "master" \
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
{ \
{ "offload0_cmd_wr_en" "CMD_WR_EN"} \
{ "offload0_cmd_wr_data" "CMD_WR_DATA"} \
{ "offload0_sdo_wr_en" "SDO_WR_EN"} \
{ "offload0_sdo_wr_data" "SDO_WR_DATA"} \
{ "offload0_enable" "ENABLE"} \
{ "offload0_enabled" "ENABLED"} \
{ "offload0_mem_reset" "MEM_RESET"} \
{ "offload_sync_ready" "SYNC_READY"} \
{ "offload_sync_valid" "SYNC_VALID"} \
{ "offload_sync_data" "SYNC_DATA"} \
{ "offload0_cmd_wr_en" "cmd_wr_en"} \
{ "offload0_cmd_wr_data" "cmd_wr_data"} \
{ "offload0_sdo_wr_en" "sdo_wr_en"} \
{ "offload0_sdo_wr_data" "sdo_wr_data"} \
{ "offload0_enable" "enable"} \
{ "offload0_enabled" "enabled"} \
{ "offload0_mem_reset" "mem_reset"} \
{ "offload_sync_ready" "sync_ready"} \
{ "offload_sync_valid" "sync_valid"} \
{ "offload_sync_data" "sync_data"} \
}

adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn"

foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} {
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41 changes: 41 additions & 0 deletions library/spi_engine/interfaces/Makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
####################################################################################
####################################################################################
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
####################################################################################

M_DEPS := interfaces_ip.tcl
M_DEPS += ../../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip_xilinx.tcl

M_VIVADO := vivado -mode batch -source

XML_FLIST := spi_engine.xml
XML_FLIST += spi_engine_rtl.xml
XML_FLIST += spi_engine_ctrl.xml
XML_FLIST += spi_engine_ctrl_rtl.xml
XML_FLIST += spi_engine_offload_ctrl.xml
XML_FLIST += spi_engine_offload_ctrl_rtl.xml

M_FLIST := *.log
M_FLIST += *.jou
M_FLIST += *.sv
M_FLIST += $(XML_FLIST)

.PHONY: all xilinx clean clean-all
all: xilinx

xilinx: $(XML_FLIST)

clean:clean-all

clean-all:
rm -rf $(M_FLIST)

%.xml: $(M_DEPS)
$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1

####################################################################################
####################################################################################
47 changes: 47 additions & 0 deletions library/spi_engine/interfaces/interfaces_ip.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,47 @@
###############################################################################
## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

# SPI interface

adi_if_define "spi_engine"
adi_if_ports output 1 sclk
adi_if_ports output 1 sdo
adi_if_ports output 1 sdo_t
adi_if_ports input -1 sdi
adi_if_ports output -1 cs
adi_if_ports output 1 three_wire

# Control interface

adi_if_define "spi_engine_ctrl"
adi_if_ports input 1 cmd_ready
adi_if_ports output 1 cmd_valid
adi_if_ports output 16 cmd_data
adi_if_ports input 1 sdo_data_ready
adi_if_ports output 1 sdo_data_valid
adi_if_ports output -1 sdo_data
adi_if_ports output 1 sdi_data_ready
adi_if_ports input 1 sdi_data_valid
adi_if_ports input -1 sdi_data
adi_if_ports output 1 sync_ready
adi_if_ports input 1 sync_valid
adi_if_ports input 8 sync_data

# Offload control interface

adi_if_define "spi_engine_offload_ctrl"
adi_if_ports output 1 cmd_wr_en
adi_if_ports output 16 cmd_wr_data
adi_if_ports output 1 sdo_wr_en
adi_if_ports output -1 sdo_wr_data
adi_if_ports output 1 mem_reset
adi_if_ports output 1 enable
adi_if_ports input 1 enabled
adi_if_ports output 1 sync_ready
adi_if_ports input 1 sync_valid
adi_if_ports input 8 sync_data
13 changes: 0 additions & 13 deletions library/spi_engine/interfaces/spi_engine_ctrl.xml

This file was deleted.

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