Adding support for arm64 arch compilation

src/shim/bo.h

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: Apache-2.0
-// Copyright (C) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
 
 #ifndef _BO_XDNA_H_
 #define _BO_XDNA_H_
@@ -16,8 +16,27 @@
 #include "drm_local/amdxdna_accel.h"
 #include <string>
 #include <atomic>
+#if defined(__x86_64__) || defined(_M_X64)
+  #include <x86intrin.h>
+#endif
 
 namespace shim_xdna {
+
+inline void flush_cache_line(const char *cur)
+{
+#if defined(__x86_64__) || defined(_M_X64)
+  _mm_clflush(cur);
+#elif defined(__aarch64__)
+  asm volatile(
+    "DC CIVAC, %[addr]\n"  // Clean and invalidate data cache
+    "DSB SY\n"             // Data Synchronization Barrier
+    "ISB SY\n"             // Instruction Synchronization Barrier
+    :
+    : [addr] "r" (cur)
+    : "memory"
+  );
+#endif
+}
 
 class bo : public xrt_core::buffer_handle
 {

src/shim/kmq/bo.cpp

@@ -1,9 +1,8 @@
 // SPDX-License-Identifier: Apache-2.0
-// Copyright (C) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+// Copyright (C) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
 
 #include "bo.h"
 #include "core/common/config_reader.h"
-#include <x86intrin.h>
 
 namespace {
 
@@ -25,7 +24,6 @@ flag_to_type(uint64_t bo_flags)
   return AMDXDNA_BO_INVALID;
 }
 
-
 // flash cache line for non coherence memory
 inline void
 clflush_data(const void *base, size_t offset, size_t len)
@@ -43,7 +41,7 @@ clflush_data(const void *base, size_t offset, size_t len)
   cur += offset;
   uintptr_t lastline = (uintptr_t)(cur + len - 1) | (cacheline_size - 1);
   do {
-    _mm_clflush(cur);
+    shim_xdna::flush_cache_line(cur);
     cur += cacheline_size;
   } while (cur <= (const char *)lastline);
 }

src/shim/umq/hwq.cpp

@@ -1,24 +1,20 @@
 // SPDX-License-Identifier: Apache-2.0
 // Copyright (C) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
 
-#include <x86intrin.h>
 #include "bo.h"
 #include "hwq.h"
 
 namespace {
 
-// flash cache line for non coherence memory
-inline void
-clflush_data(void *data, int len)
+void clflush_data(const void *data, size_t len)
 {
-	const int LINESIZE = 64;
-	const char *cur = (const char *)data;
-	// must be at least one cache line
-	uintptr_t lastline = (uintptr_t)(cur + len - 1) | (LINESIZE - 1);
-	do {
-		_mm_clflush(cur);
-		cur += LINESIZE;
-	} while (cur <= (const char *)lastline);
+  const int LINESIZE = 64;
+  const char *cur = (const char *)data;
+  uintptr_t lastline = (uintptr_t)(cur + len - 1) | (LINESIZE - 1);
+  do {
+    shim_xdna::flush_cache_line(cur);
+    cur += LINESIZE;
+  } while (cur <= (const char *)lastline);
 }
 
 inline void