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Adding support for arm64 arch compilation #367

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22 changes: 21 additions & 1 deletion src/shim/bo.h
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: Apache-2.0
// Copyright (C) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
// Copyright (C) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.

#ifndef _BO_XDNA_H_
#define _BO_XDNA_H_
Expand All @@ -16,9 +16,29 @@
#include "drm_local/amdxdna_accel.h"
#include <string>
#include <atomic>
#if defined(__x86_64__) || defined(_M_X64)
#include <x86intrin.h>
#endif

namespace shim_xdna {

const int LINESIZE = 64;

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inline void flush_cache_line(const char *cur) {
#if defined(__x86_64__) || defined(_M_X64)
_mm_clflush(cur);
#elif defined(__aarch64__)
asm volatile(
"DC CIVAC, %[addr]\n" // Clean and invalidate data cache
"DSB SY\n" // Data Synchronization Barrier
"ISB SY\n" // Instruction Synchronization Barrier
:
: [addr] "r" (cur)
: "memory"
);
#endif
}
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class bo : public xrt_core::buffer_handle
{
public:
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6 changes: 2 additions & 4 deletions src/shim/kmq/bo.cpp
Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: Apache-2.0
// Copyright (C) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
// Copyright (C) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.

#include "bo.h"
#include "core/common/config_reader.h"
#include <x86intrin.h>

namespace {

Expand All @@ -25,7 +24,6 @@ flag_to_type(uint64_t bo_flags)
return AMDXDNA_BO_INVALID;
}


// flash cache line for non coherence memory
inline void
clflush_data(const void *base, size_t offset, size_t len)
Expand All @@ -43,7 +41,7 @@ clflush_data(const void *base, size_t offset, size_t len)
cur += offset;
uintptr_t lastline = (uintptr_t)(cur + len - 1) | (cacheline_size - 1);
do {
_mm_clflush(cur);
shim_xdna::flush_cache_line(cur);
cur += cacheline_size;
} while (cur <= (const char *)lastline);
}
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20 changes: 7 additions & 13 deletions src/shim/umq/hwq.cpp
Original file line number Diff line number Diff line change
@@ -1,24 +1,18 @@
// SPDX-License-Identifier: Apache-2.0
// Copyright (C) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.

#include <x86intrin.h>
#include "bo.h"
#include "hwq.h"

namespace {

// flash cache line for non coherence memory
inline void
clflush_data(void *data, int len)
{
const int LINESIZE = 64;
const char *cur = (const char *)data;
// must be at least one cache line
uintptr_t lastline = (uintptr_t)(cur + len - 1) | (LINESIZE - 1);
do {
_mm_clflush(cur);
cur += LINESIZE;
} while (cur <= (const char *)lastline);
void clflush_data(const void *data, size_t len) {
const char *cur = (const char *)data;
uintptr_t lastline = (uintptr_t)(cur + len - 1) | (shim_xdna::LINESIZE - 1);
do {
shim_xdna::flush_cache_line(cur);
cur += shim_xdna::LINESIZE;
} while (cur <= (const char *)lastline);
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}

inline void
Expand Down