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Fix broken link to RTLIL documentation. #3

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Merged
whitequark merged 1 commit into from
Aug 1, 2024
Merged

Fix broken link to RTLIL documentation. #3

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2 changes: 1 addition & 1 deletion src/app.tsx
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Original file line number Diff line number Diff line change
Expand Up @@ -273,7 +273,7 @@ function AppContent() {
</li>
<li>
<code>amaranth_playground.show_rtlil(rtlil.convert(m))</code> displays <Link
href="https://yosyshq.readthedocs.io/projects/yosys/en/latest/CHAPTER_Overview.html#the-rtl-intermediate-language-rtlil"
href="https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/formats/rtlil_rep.html"
>RTLIL code</Link>, the <Link href="https://yosyshq.net">Yosys</Link> intermediate
representation. This code is accepted by the open-source FPGA toolchain, and is used
internally by the Amaranth compiler to produce Verilog code. Unless you are investigating
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