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| -2024-2025-project-4-web-fpga-team-4 |
| 1 | +<p align="center"><em>What if you could visualize, simulate, and master FPGA development all in one place with...</em></p> |
| 2 | +<p align="center"> |
| 3 | + <picture><source media="(prefers-color-scheme: dark)" srcset="./documents/functional-specifications/images/logo-light.png"><source media="(prefers-color-scheme: light)" srcset="./documents/functional-specifications/images/logo-dark.png"><img alt="FPGA Explorer Logo" style="width:100px"> </picture> |
| 4 | +</p> |
| 5 | +<p align="center"> |
| 6 | +<a href="#features">Features</a> • |
| 7 | +<a href="#manifest">Manifest</a> • |
| 8 | +<a href="#prerequisites">Prerequisites</a> • |
| 9 | +<a href="#configuration">Configuration</a> • |
| 10 | +<a href="#json-creator">JSON Creator</a> |
| 11 | +</p> |
| 12 | + |
| 13 | +<hr> |
| 14 | + |
| 15 | +**FPGA Explorer** is an interactive platform designed to simplify the exploration and learning of Field-Programmable Gate Arrays (FPGAs). Whether you're a student, teacher, or hobbyist, this tool helps you understand, develop, and simulate FPGA logic in a visual and intuitive way. |
| 16 | + |
| 17 | +👉 [**Try it online**](https://two024-2025-project-4-web-fpga-team-4.onrender.com/client.html) |
| 18 | + |
| 19 | +You can use the file example.sdf to test the application. |
| 20 | + |
| 21 | +You can also upload your own `.sdf` files to visualize and simulate them. |
| 22 | + |
| 23 | +# Features |
| 24 | + |
| 25 | +- **Visual Logic Simulation** |
| 26 | + Simulate FPGA circuits in real time and watch how data flows through flip-flops, LUTs, and wires—perfect for exploring internal chip behavior. |
| 27 | + |
| 28 | +- **Educational Focus** |
| 29 | + Designed for learning, FPGA Explorer makes it easy to understand digital logic by visualizing how components interact, step by step. |
| 30 | + |
| 31 | +- **Pivot Format** |
| 32 | + Upload `.sdf` files and watch them automatically parsed into a structured JSON format designed for clarity and modularity. |
| 33 | + You can download the generated JSON, tweak it, and re-upload it to create your own examples effortlessly. |
| 34 | + |
| 35 | + |
| 36 | +# Manifest |
| 37 | + |
| 38 | +- [Functional Specifications](./documents/functional-specifications/functional-specifications.md) |
| 39 | +- [Technical Specifications](./documents/technical-specifications/technical-specifications.md) |
| 40 | +- [Test Plan](./documents/quality-assurance/test-plan.md) |
| 41 | +- [User Manual](./documents/user-manual/user-manual.pdf) |
| 42 | +- [Management Artifacts](./documents/management/management-artifact.md) |
| 43 | +- [Source Code](./src/) |
| 44 | +- [SDF Example](./documents/user-manual/example.sdf) |
| 45 | +- [JSON Creator](./src/json_creator/json-creator.py) |
| 46 | + |
| 47 | +# Prerequisites |
| 48 | + |
| 49 | +- Node.js (v14 or later) |
| 50 | +- npm (Node Package Manager) |
| 51 | +- Python 3.x (for JSON Creator) |
| 52 | + |
| 53 | +# Configuration |
| 54 | + |
| 55 | +1. Clone the repository |
| 56 | +```bash |
| 57 | +git clone https://github.com/algosup/2024-2025-project-4-web-fpga-team-4.git |
| 58 | +``` |
| 59 | +2. Navigate to the directory |
| 60 | +```bash |
| 61 | +cd 2024-2025-project-4-web-fpga-team-4/src |
| 62 | +``` |
| 63 | +3. Start the application |
| 64 | +```bash |
| 65 | +npm install |
| 66 | +npm start |
| 67 | +``` |
| 68 | + |
| 69 | +The interface will open in your browser at http://localhost:8080/code/client.html. |
| 70 | + |
| 71 | +# JSON Creator |
| 72 | + |
| 73 | +FPGA Explorer includes a **command-line script** to help users generate custom `.json` files without writing them from scratch. This is ideal for testing small examples or building circuits manually. |
| 74 | + |
| 75 | +> ⚠️ Note: This tool is **optional** and not the main feature of the platform. |
| 76 | +
|
| 77 | +## Run the Script |
| 78 | + |
| 79 | +```bash |
| 80 | +/opt/homebrew/bin/python3 ./src/json_creator/json-creator.py |
| 81 | +``` |
| 82 | + |
| 83 | +It will guide you step by step through: |
| 84 | +- Adding **LUTs**, **Flip-Flops**, and **I/Os** |
| 85 | +- Creating **connections** with timing delays |
| 86 | +- Saving everything into a valid `output.json` file |
| 87 | + |
| 88 | +You can upload the generated file directly into FPGA Explorer to simulate your custom circuit. |
| 89 | + |
| 90 | +## Important Notes |
| 91 | +- **Case sensitive**: Use correct casing for element types (`LUT`, `FlipFlop`, `IO`) |
| 92 | +- **Unique IDs**: Required for LUTs and Flip-Flops |
| 93 | +- **Valid timing**: Must be a numeric value |
| 94 | +- **I/Os use names** instead of numeric IDs |
| 95 | + |
| 96 | +<!-- # Known Bugs |
| 97 | +
|
| 98 | +- [ ] Add a list of known bugs here --> |
| 99 | + |
| 100 | +# Contributing |
| 101 | +We welcome contributions! Feel free to submit issues, suggest new features, or open pull requests. |
| 102 | + |
| 103 | +# License |
| 104 | +[MIT License](./LICENSE.md) |
| 105 | + |
| 106 | +# Authors |
| 107 | + |
| 108 | +Made with ❤️ by Team 4 |
| 109 | + |
| 110 | +- [**Thibaud Marlier**](https://www.linkedin.com/in/thibaudmarlier/) – Project Manager |
| 111 | +- [**Maxime Caron**](https://www.linkedin.com/in/maxime-caron-dev/) – Program Manager |
| 112 | +- [**Emilien Chinsy**](https://www.linkedin.com/in/emilien-chinsy-5a794632b/) – Technical Lead |
| 113 | +- [**Guillaume Despaux**](https://www.linkedin.com/in/guillaume-despaux/) – Quality Assurance |
| 114 | +- [**Clémentine Curel**](https://www.linkedin.com/in/clementinecurel/) – Technical Writer |
| 115 | +- [**Jason Grosso**](https://www.linkedin.com/in/jason-grosso-847b39251/) – Software Engineer |
| 116 | +- [**Laurent Bouquin**](https://www.linkedin.com/in/laurentb22/) – Software Engineer |
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