What if you could visualize, simulate, and master FPGA development all in one place with...
Features • Manifest • Prerequisites • Configuration • JSON Creator
FPGA Explorer is an interactive platform designed to simplify the exploration and learning of Field-Programmable Gate Arrays (FPGAs). Whether you're a student, teacher, or hobbyist, this tool helps you understand, develop, and simulate FPGA logic in a visual and intuitive way.
👉 Try it online
You can use the file example.sdf to test the application.
You can also upload your own .sdf
files to visualize and simulate them.
-
Visual Logic Simulation
Simulate FPGA circuits in real time and watch how data flows through flip-flops, LUTs, and wires—perfect for exploring internal chip behavior. -
Educational Focus
Designed for learning, FPGA Explorer makes it easy to understand digital logic by visualizing how components interact, step by step. -
Pivot Format
Upload.sdf
files and watch them automatically parsed into a structured JSON format designed for clarity and modularity.
You can download the generated JSON, tweak it, and re-upload it to create your own examples effortlessly.
- Functional Specifications
- Technical Specifications
- Test Plan
- User Manual
- Management Artifacts
- Source Code
- SDF Example
- JSON Creator
- Node.js (v14 or later)
- npm (Node Package Manager)
- Python 3.x (for JSON Creator)
- Clone the repository
git clone https://github.com/algosup/2024-2025-project-4-web-fpga-team-4.git
- Navigate to the directory
cd 2024-2025-project-4-web-fpga-team-4/src
- Start the application
npm install
npm start
The interface will open in your browser at http://localhost:8080/code/client.html.
FPGA Explorer includes a command-line script to help users generate custom .json
files without writing them from scratch. This is ideal for testing small examples or building circuits manually.
⚠️ Note: This tool is optional and not the main feature of the platform.
/opt/homebrew/bin/python3 ./src/json_creator/json-creator.py
It will guide you step by step through:
- Adding LUTs, Flip-Flops, and I/Os
- Creating connections with timing delays
- Saving everything into a valid
output.json
file
You can upload the generated file directly into FPGA Explorer to simulate your custom circuit.
- Case sensitive: Use correct casing for element types (
LUT
,FlipFlop
,IO
) - Unique IDs: Required for LUTs and Flip-Flops
- Valid timing: Must be a numeric value
- I/Os use names instead of numeric IDs
We welcome contributions! Feel free to submit issues, suggest new features, or open pull requests.
Made with ❤️ by Team 4
- Thibaud Marlier – Project Manager
- Maxime Caron – Program Manager
- Emilien Chinsy – Technical Lead
- Guillaume Despaux – Quality Assurance
- Clémentine Curel – Technical Writer
- Jason Grosso – Software Engineer
- Laurent Bouquin – Software Engineer