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zephyr-cp: fix asyncio and busio.SPI on native_sim, add an SPI loopback for tests - #11504
lynt-smitka wants to merge 3 commits into
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The C part of asyncio picked its clock with a __unix__ test, meant for the unix port, which has no supervisor. Zephyr's native_sim is a host build too, so there it used mp_hal_ticks_ms() while the Python part used supervisor.ticks_ms(), which starts 65 s before its first wrap. A task from create_task() got a key 65 s ahead of a sleeping task and did not run. Test for CIRCUITPY_SUPERVISOR instead.
spi_transceive_signal() calls the driver's transceive_async without checking it, and the native_sim emulator has none, so the first busio.SPI transfer crashed there. One transceive() helper now falls back to spi_transceive(). It also frees the fill buffer of readinto() only after the transfer, which a DMA driver may still read.
…ve_sim A circuitpython,spi-loopback emulator on spi0 reads back every byte sent. On native_sim, iobroker now gives any pins the emulated SPI controller, so a bus can be constructed from pins, as on real boards. tests/test_spi.py checks busio.SPI through the loopback.
Why not add an async call to the emulator? I'd rather test the actual way we want it to work. |
The emulator is zephyr's |
Yup, feel free to change adafruit/zephyr. I've done a bunch around perfetto tracing there already. |
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@tannewt I made PR to zephyr with spi emulator adafruit/zephyr#8, then we can finish this one and continue on #11489 🙂 |
This PR fixes two bugs on native_sim and adds a way to test SPI there. It is the prerequisite to continue work on #11489.
asyncio.create_task()did not run on native_sim. extmod/modasyncio.c picked its clock with a unix test, which is also true for native_sim, so the C and Python parts of asyncio used clocks 65 s apart. It now tests CIRCUITPY_SUPERVISOR.busio.SPIcrashed on native_sim: the SPI emulator has no transceive_async. busio now uses the blocking spi_transceive() when a driver has no async path.