zephyr-cp: add the Silicon Labs SiWx917-DK2605A - #11218
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I doubt we actually need the "elf" portion here if rps is used for loading. |
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Agreed, dropped it. Checked that this does not cost debugging. Rebuilt clean with Separate thing I should flag on this PR, since it is not ready yet and it is why this is still a draft. because vendor_index = zephyr_board_dir.parent / "index.rst"That holds for I would rather fix that generically than hand-edit a generated file. Happy to send it as its own PR like the gpio-keys one, unless you would rather it rode along here. |
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Rebuilt with the The name in that file needs #11220 to stay correct across a rebuild, otherwise the generator rewrites it to "Dev Kits and Thunderboards SiWx917 ...". Built once from So this now waits on two: #11210 to build at all, and #11220 for the board's published name. |
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Rebased onto Built from merged upstream with only this branch and #11220 applied, then flashed to two SiWx917-DK2605A boards on separate hosts:
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tannewt
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A couple suggestions to make this more concise.
| CONFIG_BT=y | ||
| CONFIG_BT_PERIPHERAL=y | ||
| CONFIG_BT_CENTRAL=y | ||
| CONFIG_BT_BROADCASTER=y | ||
| CONFIG_BT_OBSERVER=y | ||
| CONFIG_BT_EXT_ADV=y | ||
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| CONFIG_BT_DEVICE_APPEARANCE_DYNAMIC=y | ||
| CONFIG_BT_DEVICE_NAME_DYNAMIC=y | ||
| CONFIG_BT_DEVICE_NAME_MAX=28 | ||
| CONFIG_BT_L2CAP_TX_MTU=253 | ||
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I believe these settings have been factored out. Maybe into Kconfig. I don't think you need them here.
| // The 8 MB PSRAM at 0xa000000 works as memory: sparse writes across a 64 KB | ||
| // buffer verify correctly and a 64 KB allocation succeeds. But using it as the | ||
| // Python heap corrupts objects under sustained allocation, and the failure is | ||
| // not about large buffers - a plain `for i in range(200000): s = s + i` with no | ||
| // buffer at all hangs the board. Symptoms are corrupted objects: an int that | ||
| // became a function, a bytearray with a wrong length, and an MPU fault calling | ||
| // a garbage pointer read from PSRAM: | ||
| // | ||
| // ***** MPU FAULT ***** Instruction Access Violation | ||
| // r0/a1: 0x0a0012c0 r12/ip: 0x0a0031ac <- PSRAM pointers | ||
| // PC: 0x410e29c8 <- called through r3, garbage | ||
| // | ||
| // Not a timing problem: identical at fast-freq 144 MHz and 33 MHz. Not the | ||
| // NWP-reserved/DMA pools either; excluding those (supervisor/port.c minimum | ||
| // region size) did not help. | ||
| // | ||
| // ROOT CAUSE FOUND 2026-08-01, and the node is enabled again. | ||
| // | ||
| // The SoC has a 16 KB data cache dedicated to PSRAM (family RM rev 1.2 section | ||
| // 5.4.5) at 0x44040000, on the QSPI2 path. The bootloader leaves it enabled and | ||
| // half-configured, and nothing in this build maintains it - see the long | ||
| // comment in supervisor/port.c, which disables it in port_heap_init() before | ||
| // any TLSF pool exists. | ||
| // | ||
| // Note what did NOT work, so it is not retried: setting ATTR_MPU_RAM_NOCACHE on | ||
| // this node changes nothing. That is an MPU attribute governing the Cortex-M | ||
| // architectural cache, and CPU_HAS_DCACHE is never selected, so there is | ||
| // nothing there for it to govern. The cache that matters is a separate | ||
| // peripheral and an MPU attribute does not reach it. |
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I don't think you need this here.
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Both done, and I took your two comments as the general rule rather than the specific instances, so this went further than the lines you marked. Rebased onto current main, so #11220 is in.
Settings the port already provides. 23 of them, not just the BT block: the Two real overrides remain, each with a reason: Comments. Removed the
TestingTwo DK2605A boards on separate hosts, same image, flashed with commander.
Not tested here: web workflow, since neither board has credentials in this build. Wi-Fi scanning returns 0 networks, which is #11223 and not specific to this board. AI assistance was used. The hardware runs are mine, and I verified the config removals against the built |
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The SiWx917 SoC pairs a Cortex-M4 application core with a separate network processor that owns the Wi-Fi and BLE radios. Firmware is loaded as an .rps container rather than a hex image, so the port's release-artifact rule gains a firmware.rps target and the board declares CIRCUITPY_BUILD_EXTENSIONS = ["rps"].
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What
Adds the CircuitPython board definition for the Silicon Labs SiWx917-DK2605A (SiWx917 Wi-Fi 6 and Bluetooth LE Dev Kit), Zephyr board
siwx917_dk2605a, SoCSiWG917M111MGTBA.The Zephyr board already exists upstream at
boards/silabs/dev_kits/siwx917_dk2605a, so this is only the CircuitPython side: the board.confand.overlayfragments,autogen_board_info.toml,circuitpython.toml, and one alias line.The .rps artifact
This SoC boots from a
.rpscontainer that the bootloader installs, not from a raw image written to an address. Zephyr'ssoc/silabs/silabs_siwx91xhandles that by leavingBUILD_OUTPUT_HEXunset and pointing the runner'sbin_fileatzephyr.rps:The port's Makefile only knew
.elf,.hex,.exeand.uf2, so a build with no.hexfailed the release-artifact copy. This adds afirmware.rpsrule and has the board declare["elf", "rps"].That matters beyond tidiness: if the board forces
CONFIG_BUILD_OUTPUT_HEX=yto satisfy the old Makefile,west flashthen prefers the.hex, reports success, and leaves a board that does not boot.Testing
Two SiWx917-DK2605A boards, on separate hosts, both flashed with the image built from this branch.
b9d03f12f(upstreammain), Zephyr at the pinned62e7a3764Artifacts produced, confirming the
.hexis correctly absent:Both boards boot:
The banner reports
BRD2605A, the radio board number, for the same kit.Board-generated pin names come from
zephyr,codevia #11210, and the pins work:west flashselects the right artifact on its own, with no arguments beyond the debugger id my bench needs because several probes are attached:and the board comes up afterwards.
make flashpasses no runner arguments, so on a host with a single debugger attached it is the same path.Wi-Fi is deliberately not in this PR. The board boots, exposes its pins and runs code without it. An implementation exists on a branch, roughly 800 lines across
ports/zephyr-cp/common-hal/wifi/, and I am holding it back rather than attaching it to a board PR: it is a behaviour change that deserves its own review, and some of it currently compensates incommon-halfor driver behaviour, which may not be the shape you want. Happy to send it next, split however you prefer.Scope
One new board plus the
firmware.rpsrule the port needs to support it. No behavior change for existing boards.AI assistance
Written with Claude Code. I ran the hardware myself. The banners, artifact listing and REPL output above are from the boards, not from a model.