WCH: Add support for CH32V307 chip and CH32V307V-R1-1v0 board (#383)

ZigEmbeddedGroup · Feb 12, 2025 · 86df0aa · 86df0aa
1 parent a413e29
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diff --git a/examples/wch/ch32v/build.zig b/examples/wch/ch32v/build.zig
@@ -28,6 +28,11 @@ pub fn build(b: *std.Build) void {
         .{ .target = mb.ports.ch32v.chips.ch32v203x8, .name = "empty_ch32v203", .file = "src/empty.zig" },
         .{ .target = mb.ports.ch32v.chips.ch32v203x8, .name = "blinky_ch32v203", .file = "src/blinky.zig" },
         .{ .target = mb.ports.ch32v.boards.ch32v203.suzuduino_uno_v1b, .name = "suzuduino_blinky", .file = "src/board_blinky.zig" },
+
+        // CH32V307
+        .{ .target = mb.ports.ch32v.chips.ch32v307xc, .name = "empty_ch32v307", .file = "src/empty.zig" },
+        .{ .target = mb.ports.ch32v.chips.ch32v307xc, .name = "blinky_ch32v307", .file = "src/blinky.zig" },
+        .{ .target = mb.ports.ch32v.boards.ch32v307.ch32v307v_r1_1v0, .name = "ch32v307v_r1_1v0_blinky", .file = "src/blinky.zig" },
     };
 
     for (available_examples) |example| {

diff --git a/port/wch/ch32v/build.zig b/port/wch/ch32v/build.zig
@@ -11,6 +11,7 @@ chips: struct {
     ch32v103x8: *const microzig.Target,
     ch32v203x6: *const microzig.Target,
     ch32v203x8: *const microzig.Target,
+    ch32v307xc: *const microzig.Target,
 },
 
 boards: struct {
@@ -23,6 +24,9 @@ boards: struct {
     ch32v203: struct {
         suzuduino_uno_v1b: *const microzig.Target,
     },
+    ch32v307: struct {
+        ch32v307v_r1_1v0: *const microzig.Target,
+    },
 },
 
 pub fn init(dep: *std.Build.Dependency) Self {
@@ -37,6 +41,9 @@ pub fn init(dep: *std.Build.Dependency) Self {
     const hal_ch32v203: microzig.HardwareAbstractionLayer = .{
         .root_source_file = b.path("src/hals/hal_ch32v203.zig"),
     };
+    const hal_ch32v307: microzig.HardwareAbstractionLayer = .{
+        .root_source_file = b.path("src/hals/hal_ch32v307.zig"),
+    };
 
     const qingkev2a = .{
         // QingKe V2C is RV32EC
@@ -77,6 +84,20 @@ pub fn init(dep: *std.Build.Dependency) Self {
         .abi = .eabi,
     };
 
+    const qingkev4f = .{
+        .cpu_arch = .riscv32,
+        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+        // generic_rv32 has feature I.
+        .cpu_features_add = std.Target.riscv.featureSet(&.{
+            std.Target.riscv.Feature.c,
+            std.Target.riscv.Feature.a,
+            std.Target.riscv.Feature.m,
+            std.Target.riscv.Feature.f,
+        }),
+        .os_tag = .freestanding,
+        .abi = .eabi,
+    };
+
     const chip_ch32v003x4: microzig.Target = .{
         .dep = dep,
         .preferred_binary_format = .bin,
@@ -168,6 +189,30 @@ pub fn init(dep: *std.Build.Dependency) Self {
         .hal = hal_ch32v203,
     };
 
+    const chip_ch32v307xc = microzig.Target{
+        .dep = dep,
+        .preferred_binary_format = .bin,
+        .chip = .{
+            .name = "CH32V30xxx", // <name/> from SVD
+            .cpu = qingkev4f,
+            .cpu_module_file = b.path("src/cpus/qingkev4-rv32imac.zig"),
+            .memory_regions = &.{
+                // FLASH + RAM supports the following configuration
+                // FLASH-192K + RAM-128K
+                // FLASH-224K + RAM-96K
+                // FLASH-256K + RAM-64K
+                // FLASH-288K + RAM-32K
+                // FLASH-128K + RAM-192K
+                .{ .offset = 0x08000000, .length = 128 * KiB, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 32 * KiB, .kind = .ram },
+            },
+            .register_definition = .{
+                .svd = b.path("src/chips/ch32v30x.svd"),
+            },
+        },
+        .hal = hal_ch32v307,
+    };
+
     const board_ch32v003f4p6_r0_1v1 = chip_ch32v003x4.derive(.{
         .board = .{
             .name = "WCH CH32V003F4P6-R0-1v1",
@@ -192,13 +237,22 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
     });
 
+    const board_ch32v307v_r1_1v0 = chip_ch32v307xc.derive(.{
+        .board = .{
+            .name = "WCH CH32V307V-R1-1V0",
+            .url = "https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0",
+            .root_source_file = b.path("src/boards/CH32V307V-R1-1v0.zig"),
+        },
+    });
+
     return .{
         .chips = .{
             .ch32v003x4 = chip_ch32v003x4.derive(.{}),
             .ch32v103x6 = chip_ch32v103x6.derive(.{}),
             .ch32v103x8 = chip_ch32v103x8.derive(.{}),
             .ch32v203x6 = chip_ch32v203x6.derive(.{}),
             .ch32v203x8 = chip_ch32v203x8.derive(.{}),
+            .ch32v307xc = chip_ch32v307xc.derive(.{}),
         },
 
         .boards = .{
@@ -211,6 +265,9 @@ pub fn init(dep: *std.Build.Dependency) Self {
             .ch32v203 = .{
                 .suzuduino_uno_v1b = board_suzuduino_uno_v1b,
             },
+            .ch32v307 = .{
+                .ch32v307v_r1_1v0 = board_ch32v307v_r1_1v0,
+            },
         },
     };
 }

diff --git a/port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig b/port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig
@@ -0,0 +1,6 @@
+// CH32V307V_MINI
+// CH32V307
+pub const chip = @import("chip");
+pub const micro = @import("microzig");
+
+pub const cpu_frequency = 8_000_000; // 8 MHz