Add $stop to documentation

Signed-off-by: Clifford Wolf <[email protected]>

README.md

@@ -416,9 +416,10 @@ Verilog Attributes and non-standard features
   expressions as <size>. If the expression is not a simple identifier, it
   must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
 
-- The system tasks ``$finish`` and ``$display`` are supported in initial blocks
-  in an unconditional context (only if/case statements on parameters
-  and constant values). The intended use for this is synthesis-time DRC.
+- The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in
+  initial blocks in an unconditional context (only if/case statements on
+  expressions over parameters and constant values are allowed). The intended
+  use for this is synthesis-time DRC.
 
 - There is limited support for converting specify .. endspecify statements to
   special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in