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Support variants for ECP5 #1154

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3 changes: 2 additions & 1 deletion common/kernel/command.cc
Original file line number Diff line number Diff line change
Expand Up @@ -97,14 +97,15 @@ bool CommandHandler::executeBeforeContext()
<< " -- Next Generation Place and Route (Version " GIT_DESCRIBE_STR ")\n";
return true;
}
validate();

if (vm.count("quiet")) {
log_streams.push_back(std::make_pair(&std::cerr, LogLevel::WARNING_MSG));
} else {
log_streams.push_back(std::make_pair(&std::cerr, LogLevel::LOG_MSG));
}

validate();

if (vm.count("Werror")) {
log_warn_as_error = true;
}
Expand Down
292 changes: 141 additions & 151 deletions ecp5/arch.cc

Large diffs are not rendered by default.

141 changes: 85 additions & 56 deletions ecp5/arch.h
Original file line number Diff line number Diff line change
Expand Up @@ -169,6 +169,28 @@ NPNR_PACKED_STRUCT(struct SpeedGradePOD {
RelSlice<PipDelayPOD> pip_classes;
});

NPNR_PACKED_STRUCT(struct PackageSupportedPOD {
RelPtr<char> name;
RelPtr<char> short_name;
});

NPNR_PACKED_STRUCT(struct SuffixeSupportedPOD { RelPtr<char> suffix; });

NPNR_PACKED_STRUCT(struct SpeedSupportedPOD { int32_t speed; });

NPNR_PACKED_STRUCT(struct VariantInfoPOD {
RelPtr<char> name;
RelSlice<PackageSupportedPOD> packages;
RelSlice<SpeedSupportedPOD> speed_grades;
RelSlice<SuffixeSupportedPOD> suffixes;
});

NPNR_PACKED_STRUCT(struct DeviceInfoPOD {
RelPtr<char> family;
RelPtr<char> name;
RelSlice<VariantInfoPOD> variants;
});

NPNR_PACKED_STRUCT(struct ChipInfoPOD {
int32_t width, height;
int32_t num_tiles;
Expand All @@ -181,6 +203,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
RelSlice<PIOInfoPOD> pio_info;
RelSlice<TileInfoPOD> tile_info;
RelSlice<SpeedGradePOD> speed_grades;
RelSlice<DeviceInfoPOD> devices;
});

/************************ End of chipdb section. ************************/
Expand Down Expand Up @@ -394,28 +417,7 @@ struct PipRange

struct ArchArgs
{
enum ArchArgsTypes
{
NONE,
LFE5U_12F,
LFE5U_25F,
LFE5U_45F,
LFE5U_85F,
LFE5UM_25F,
LFE5UM_45F,
LFE5UM_85F,
LFE5UM5G_25F,
LFE5UM5G_45F,
LFE5UM5G_85F,
} type = NONE;
std::string package;
enum SpeedGrade
{
SPEED_6 = 0,
SPEED_7,
SPEED_8,
SPEED_8_5G,
} speed = SPEED_6;
std::string device;
};

struct DelayKey
Expand Down Expand Up @@ -444,11 +446,40 @@ struct ArchRanges : BaseArchRanges
using AllPipsRangeT = AllPipRange;
};

struct Arch : BaseArch<ArchRanges>
{
struct ArchDevice {
const DeviceInfoPOD *device_info;
const ChipInfoPOD *chip_info;
const PackageInfoPOD *package_info;
const SpeedGradePOD *speed_grade;
const char *package_name;
const char *device_name;
enum ArchTypes
{
NONE,
LFE5U_12F,
LFE5U_25F,
LFE5U_45F,
LFE5U_85F,
LFE5UM_25F,
LFE5UM_45F,
LFE5UM_85F,
LFE5UM5G_25F,
LFE5UM5G_45F,
LFE5UM5G_85F,
} type = NONE;

enum SpeedGrade
{
SPEED_6 = 0,
SPEED_7,
SPEED_8,
SPEED_8_5G,
} speed = SPEED_6;
};

struct Arch : BaseArch<ArchRanges>
{
ArchDevice device;

mutable dict<IdStringList, PipId> pip_by_name;

Expand Down Expand Up @@ -513,11 +544,9 @@ struct Arch : BaseArch<ArchRanges>
ArchArgs args;
Arch(ArchArgs args);

static bool is_available(ArchArgs::ArchArgsTypes chip);
static std::vector<std::string> get_supported_packages(ArchArgs::ArchArgsTypes chip);
static void list_devices();

std::string getChipName() const override;
std::string get_full_chip_name() const;

ArchArgs archArgs() const override { return args; }
IdString archArgsToId(ArchArgs args) const override;
Expand All @@ -526,8 +555,8 @@ struct Arch : BaseArch<ArchRanges>

static const int max_loc_bels = 32;

int getGridDimX() const override { return chip_info->width; };
int getGridDimY() const override { return chip_info->height; };
int getGridDimX() const override { return device.chip_info->width; };
int getGridDimY() const override { return device.chip_info->height; };
int getTileBelDimZ(int, int) const override { return max_loc_bels; };
int getTilePipDimZ(int, int) const override { return 1; };
char getNameDelimiter() const override { return '/'; }
Expand All @@ -538,12 +567,12 @@ struct Arch : BaseArch<ArchRanges>

template <typename Id> const LocationTypePOD *loc_info(Id &id) const
{
return &(chip_info->locations[chip_info->location_type[id.location.y * chip_info->width + id.location.x]]);
return &(device.chip_info->locations[device.chip_info->location_type[id.location.y * device.chip_info->width + id.location.x]]);
}

template <typename Id> inline int tile_index(Id id) const
{
return id.location.y * chip_info->width + id.location.x;
return id.location.y * device.chip_info->width + id.location.x;
}

IdStringList getBelName(BelId bel) const override
Expand All @@ -559,7 +588,7 @@ struct Arch : BaseArch<ArchRanges>
int get_slice_index(int x, int y, int slice) const
{
NPNR_ASSERT(slice >= 0 && slice < 4);
return (y * chip_info->width + x) * 4 + slice;
return (y * device.chip_info->width + x) * 4 + slice;
}

void update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell)
Expand Down Expand Up @@ -650,11 +679,11 @@ struct Arch : BaseArch<ArchRanges>
BelRange range;
range.b.cursor_tile = 0;
range.b.cursor_index = -1;
range.b.chip = chip_info;
range.b.chip = device.chip_info;
++range.b; //-1 and then ++ deals with the case of no Bels in the first tile
range.e.cursor_tile = chip_info->width * chip_info->height;
range.e.cursor_tile = device.chip_info->width * device.chip_info->height;
range.e.cursor_index = 0;
range.e.chip = chip_info;
range.e.chip = device.chip_info;
return range;
}

Expand Down Expand Up @@ -707,7 +736,7 @@ struct Arch : BaseArch<ArchRanges>

uint32_t get_wire_vecidx(const WireId &e) const
{
uint32_t tile = e.location.y * chip_info->width + e.location.x;
uint32_t tile = e.location.y * device.chip_info->width + e.location.x;
int32_t base = wire_tile_vecidx.at(tile);
NPNR_ASSERT(base != -1);
int32_t i = base + e.index;
Expand Down Expand Up @@ -754,11 +783,11 @@ struct Arch : BaseArch<ArchRanges>
WireRange range;
range.b.cursor_tile = 0;
range.b.cursor_index = -1;
range.b.chip = chip_info;
range.b.chip = device.chip_info;
++range.b; //-1 and then ++ deals with the case of no wries in the first tile
range.e.cursor_tile = chip_info->width * chip_info->height;
range.e.cursor_tile = device.chip_info->width * device.chip_info->height;
range.e.cursor_index = 0;
range.e.chip = chip_info;
range.e.chip = device.chip_info;
return range;
}

Expand Down Expand Up @@ -786,7 +815,7 @@ struct Arch : BaseArch<ArchRanges>

uint32_t get_pip_vecidx(const PipId &e) const
{
uint32_t tile = e.location.y * chip_info->width + e.location.x;
uint32_t tile = e.location.y * device.chip_info->width + e.location.x;
int32_t base = pip_tile_vecidx.at(tile);
NPNR_ASSERT(base != -1);
int32_t i = base + e.index;
Expand Down Expand Up @@ -859,11 +888,11 @@ struct Arch : BaseArch<ArchRanges>
AllPipRange range;
range.b.cursor_tile = 0;
range.b.cursor_index = -1;
range.b.chip = chip_info;
range.b.chip = device.chip_info;
++range.b; //-1 and then ++ deals with the case of no wries in the first tile
range.e.cursor_tile = chip_info->width * chip_info->height;
range.e.cursor_tile = device.chip_info->width * device.chip_info->height;
range.e.cursor_index = 0;
range.e.chip = chip_info;
range.e.chip = device.chip_info;
return range;
}

Expand All @@ -890,11 +919,11 @@ struct Arch : BaseArch<ArchRanges>
NPNR_ASSERT(pip != PipId());
int fanout = wire_fanout[get_wire_vecidx(getPipSrcWire(pip))];
delay_t min_dly =
speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_base_delay +
fanout * speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_fanout_adder;
device.speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_base_delay +
fanout * device.speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_fanout_adder;
delay_t max_dly =
speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].max_base_delay +
fanout * speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].max_fanout_adder;
device.speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].max_base_delay +
fanout * device.speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].max_fanout_adder;
return DelayQuad(min_dly, max_dly);
}

Expand Down Expand Up @@ -922,7 +951,7 @@ struct Arch : BaseArch<ArchRanges>

std::string get_pip_tilename(PipId pip) const
{
auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x];
auto &tileloc = device.chip_info->tile_info[pip.location.y * device.chip_info->width + pip.location.x];
for (auto &tn : tileloc.tile_names) {
if (tn.type_idx == loc_info(pip)->pip_data[pip.index].tile_type)
return tn.name.get();
Expand All @@ -932,7 +961,7 @@ struct Arch : BaseArch<ArchRanges>

std::string get_pip_tiletype(PipId pip) const
{
return chip_info->tiletype_names[loc_info(pip)->pip_data[pip.index].tile_type].get();
return device.chip_info->tiletype_names[loc_info(pip)->pip_data[pip.index].tile_type].get();
}

Loc getPipLocation(PipId pip) const override
Expand Down Expand Up @@ -1021,9 +1050,9 @@ struct Arch : BaseArch<ArchRanges>
std::vector<std::pair<std::string, std::string>> get_tiles_at_loc(int row, int col);
std::string get_tile_by_type_loc(int row, int col, std::string type) const
{
auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
auto &tileloc = device.chip_info->tile_info[row * device.chip_info->width + col];
for (auto &tn : tileloc.tile_names) {
if (chip_info->tiletype_names[tn.type_idx].get() == type)
if (device.chip_info->tiletype_names[tn.type_idx].get() == type)
return tn.name.get();
}
NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type " +
Expand All @@ -1032,20 +1061,20 @@ struct Arch : BaseArch<ArchRanges>

std::string get_tile_by_type_loc(int row, int col, const std::set<std::string> &type) const
{
auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
auto &tileloc = device.chip_info->tile_info[row * device.chip_info->width + col];
for (auto &tn : tileloc.tile_names) {
if (type.count(chip_info->tiletype_names[tn.type_idx].get()))
if (type.count(device.chip_info->tiletype_names[tn.type_idx].get()))
return tn.name.get();
}
NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set");
}

std::string get_tile_by_type(std::string type) const
{
for (int i = 0; i < chip_info->height * chip_info->width; i++) {
auto &tileloc = chip_info->tile_info[i];
for (int i = 0; i < device.chip_info->height * device.chip_info->width; i++) {
auto &tileloc = device.chip_info->tile_info[i];
for (auto &tn : tileloc.tile_names)
if (chip_info->tiletype_names[tn.type_idx].get() == type)
if (device.chip_info->tiletype_names[tn.type_idx].get() == type)
return tn.name.get();
}
NPNR_ASSERT_FALSE_STR("no tile with type " + type);
Expand Down
4 changes: 2 additions & 2 deletions ecp5/arch_place.cc
Original file line number Diff line number Diff line change
Expand Up @@ -188,8 +188,8 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
if (cell == nullptr) {
return true;
} else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) {
return args.type != ArchArgs::LFE5U_25F && args.type != ArchArgs::LFE5U_45F &&
args.type != ArchArgs::LFE5U_85F;
return device.type != ArchDevice::LFE5U_25F && device.type != ArchDevice::LFE5U_45F &&
device.type != ArchDevice::LFE5U_85F;
} else if (cell->type.in(id_MULT18X18D, id_ALU54B)) {
return is_dsp_location_valid(cell);
} else {
Expand Down
2 changes: 1 addition & 1 deletion ecp5/arch_pybindings.cc
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ NEXTPNR_NAMESPACE_BEGIN
void arch_wrap_python(py::module &m)
{
using namespace PythonConversion;
py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("type", &ArchArgs::type);
py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("device", &ArchArgs::device);

py::class_<BelId>(m, "BelId").def_readwrite("index", &BelId::index);

Expand Down
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