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Add arch API function for pip inversion
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Ravenslofty committed Feb 3, 2025
1 parent e4115e8 commit 0020877
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Showing 6 changed files with 28 additions and 3 deletions.
1 change: 1 addition & 0 deletions common/kernel/arch_api.h
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual WireId getPipDstWire(PipId pip) const = 0;
virtual DelayQuad getPipDelay(PipId pip) const = 0;
virtual Loc getPipLocation(PipId pip) const = 0;
virtual bool isPipInverting(PipId pip) const = 0;
// Group methods
virtual GroupId getGroupByName(IdStringList name) const = 0;
virtual IdStringList getGroupName(GroupId group) const = 0;
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1 change: 1 addition & 0 deletions common/kernel/base_arch.h
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Expand Up @@ -288,6 +288,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
}
virtual WireId getConflictingPipWire(PipId /*pip*/) const override { return WireId(); }
virtual NetInfo *getConflictingPipNet(PipId pip) const override { return getBoundPipNet(pip); }
virtual bool isPipInverting(PipId /*pip*/) const override { return false; }

// Group methods
virtual GroupId getGroupByName(IdStringList /*name*/) const override { return GroupId(); };
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6 changes: 6 additions & 0 deletions docs/archapi.md
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Expand Up @@ -417,6 +417,12 @@ pip is already bound to that net.

*BaseArch default: returns `getBoundPipNet(pip) == nullptr || getBoundPipNet(pip) == net`*

### bool isPipInverting(PipId pip) const

Returns true if the given pip inverts the net passing through it.

*BaseArch default: returns `false`*

### NetInfo \*getBoundPipNet(PipId pip) const

Return the net this pip is bound to.
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19 changes: 16 additions & 3 deletions himbaechel/arch.cc
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Expand Up @@ -285,13 +285,19 @@ IdStringList Arch::getWireName(WireId wire) const

PipId Arch::getPipByName(IdStringList name) const
{
NPNR_ASSERT(name.size() == 3);
NPNR_ASSERT(name.size() == 3 || (name.size() == 4 && name[4] == getCtx()->id("INV")));
int tile = tile_name2idx.at(name[0]);
const auto &tdata = chip_tile_info(chip_info, tile);
for (int pip = 0; pip < tdata.pips.ssize(); pip++) {
if (IdString(tdata.wires[tdata.pips[pip].dst_wire].name) == name[1] &&
IdString(tdata.wires[tdata.pips[pip].src_wire].name) == name[2])
return PipId(tile, pip);
IdString(tdata.wires[tdata.pips[pip].src_wire].name) == name[2]) {

auto tmp_pip = PipId(tile, pip);
if ((name.size() == 3 && !getCtx()->isPipInverting(tmp_pip)) ||
(name.size() == 4 && getCtx()->isPipInverting(tmp_pip))) {
return tmp_pip;
}
}
}
return PipId();
}
Expand All @@ -300,6 +306,13 @@ IdStringList Arch::getPipName(PipId pip) const
{
auto &tdata = chip_tile_info(chip_info, pip.tile);
auto &pdata = tdata.pips[pip.index];
if (getCtx()->isPipInverting(pip)) {
// TODO: variadic IdStringList::concat? this is messy.
return IdStringList::concat(tile_name.at(pip.tile),
IdStringList::concat(IdString(tdata.wires[pdata.dst_wire].name),
IdStringList::concat(IdString(tdata.wires[pdata.src_wire].name),
getCtx()->id("INV"))));
}
return IdStringList::concat(tile_name.at(pip.tile),
IdStringList::concat(IdString(tdata.wires[pdata.dst_wire].name),
IdString(tdata.wires[pdata.src_wire].name)));
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3 changes: 3 additions & 0 deletions himbaechel/arch.h
Original file line number Diff line number Diff line change
Expand Up @@ -662,6 +662,9 @@ struct Arch : BaseArch<ArchRanges>
uarch->notifyPipChange(pip, nullptr);
BaseArch::unbindPip(pip);
}
bool isPipInverting(PipId pip) const override {
return uarch->isPipInverting(pip);
}

// -------------------------------------------------

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1 change: 1 addition & 0 deletions himbaechel/himbaechel_api.h
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Expand Up @@ -89,6 +89,7 @@ struct HimbaechelAPI
virtual bool checkWireAvail(WireId wire) const { return true; }
virtual bool checkPipAvail(PipId pip) const { return true; }
virtual bool checkPipAvailForNet(PipId pip, const NetInfo *net) const { return checkPipAvail(pip); };
virtual bool isPipInverting(PipId pip) const { return false; }

// --- Route lookahead ---
virtual delay_t estimateDelay(WireId src, WireId dst) const;
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