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fix clk_wiz divisor calculation #356

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fix clk_wiz divisor calculation #356

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8 changes: 0 additions & 8 deletions XilinxProcessorIPLib/drivers/clk_wiz/src/xclk_wiz.c
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Original file line number Diff line number Diff line change
Expand Up @@ -171,11 +171,7 @@ static u32 XClk_Wiz_CalculateDivisors (XClk_Wiz *InstancePtr, u64 SetRate)

for (m = Mmin; m <= Mmax; m++) {
for (d = Dmin; d <= Dmax; d++) {
#ifndef SDT
Fvco = InstancePtr->Config.PrimInClkFreq * m / d;
#else
Fvco = InstancePtr->Config.PrimInClkFreq * m / (d * XCLK_MHZ);
#endif
if ( Fvco >= VcoMin && Fvco <= VcoMax ) {

for (Div = Omin; Div <= Omax; Div++ ) {
Expand Down Expand Up @@ -268,11 +264,7 @@ static u32 XClk_Wiz_CalculateDivisorsHz (XClk_Wiz *InstancePtr, u64 SetRate)

for (m = Mmin; m <= Mmax; m++) {
for (d = Dmin; d <= Dmax; d++) {
#ifndef SDT
Fvco = InstancePtr->Config.PrimInClkFreq * XCLK_MHZ * m / d;
#else
Fvco = InstancePtr->Config.PrimInClkFreq * m / d;
#endif
if ( Fvco >= VcoMin * XCLK_MHZ && Fvco <= VcoMax * XCLK_MHZ ) {

for (Div = Omin; Div <= Omax; Div++ ) {
Expand Down