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add spare reg to status
- #32
#32
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hackwa
merged 2 commits into
Xilinx:main
Xilinx/MLDebugger:main
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hackwa:sparereg
hackwa/MLDebugger:sparereg
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Jul 22, 2026
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add spare reg to status
#32
hackwa
merged 2 commits into
Xilinx:main
Xilinx/MLDebugger:main
from
hackwa:sparereg
hackwa/MLDebugger:sparereg
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Commits on Jul 22, 2026
add spare reg to status
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anurag
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fix spacing
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anurag
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960fc56
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anurag