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[MIPS] Mark jalr[.hb] $zero, $ra as a return instruction #7356

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[MIPS] Mark jalr[.hb] $zero, $ra as a return instruction #7356

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6 changes: 4 additions & 2 deletions arch/mips/arch_mips.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -332,10 +332,12 @@ class MipsArchitecture: public Architecture
result.AddBranch(CallDestination, instr.operands[0].immediate, nullptr, hasBranchDelay);
break;

//Jmp to register register value is unknown
case MIPS_JALR:
case MIPS_JALR_HB:
result.delaySlots = 1;
if (instr.operands[0].reg == REG_ZERO && instr.operands[1].reg == REG_RA)
result.AddBranch(FunctionReturn, 0, nullptr, hasBranchDelay);
else
result.AddBranch(UnresolvedBranch, 0, nullptr, hasBranchDelay);
break;

case MIPS_BGEZAL:
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5 changes: 4 additions & 1 deletion arch/mips/il.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1430,7 +1430,10 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
{
operand = 2;
}
il.AddInstruction(il.Call(ReadILOperand(il, instr, operand, registerSize(instr.operands[operand]), addrSize, true)));
if (operand == 2 && op1.reg == REG_ZERO && op2.reg == REG_RA)
il.AddInstruction(il.Return(il.Register(addrSize, REG_RA)));
else
il.AddInstruction(il.Call(ReadILOperand(il, instr, operand, registerSize(instr.operands[operand]), addrSize, true)));
}
break;
case MIPS_JR:
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