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Pull requests: SpinalHDL/SpinalHDL

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Pull requests list

Improve assignment overlap error message with previous location
#1700 opened Apr 7, 2025 by pluveto Loading…
2 tasks
[core/Mem] Add initialContent element null value check and improve error message
#1699 opened Apr 7, 2025 by pluveto Loading…
Add "at " in front of spinal error trace to be similar to java trace
#1698 opened Apr 6, 2025 by mrcmry Loading…
Improve error reporting by adding assignment details for "hardware assignments outside components" error
#1697 opened Apr 6, 2025 by pluveto Loading…
Add method to return a seq of tags of a given type
#1696 opened Apr 5, 2025 by jdavidberger Loading…
1
Fix strb of Axi4Master (spinal.lib.bus.amba4.axi.sim)
#1692 opened Mar 26, 2025 by Nik-Sch Loading…
2 tasks done
6
register Stream.s2mPipe.rData when necessary to save power
#1689 opened Mar 24, 2025 by facebreeze Loading…
2 tasks
4
add initialize argument to StreamFifo
#1680 opened Mar 13, 2025 by facebreeze Loading…
2 tasks
8
Create IMasterSlaveDirDeclare
#1676 opened Mar 11, 2025 by g0t00 Loading…
1 of 2 tasks
4
Interface-related SystemVerilog Code Emission Enhancements
#1631 opened Dec 23, 2024 by fl4shk • Draft
2 tasks
4
Fix simulation failure with Verilator v5.x on Windows
#1618 opened Dec 10, 2024 by du33169 Loading…
2 tasks
1
7
Make 2.11 & 2.13 CI test always.
#1589 opened Nov 5, 2024 by Readon • Draft
1 task
2
fix test initial value problem for Dfi Controller.
#1581 opened Oct 29, 2024 by Readon Loading…
2 tasks
1
Add mill template link to readme
#1505 opened Aug 13, 2024 by mrcmry Loading…
2
Add SamplerCC pushCd(reg) -> popCd(BufferCC)
#1500 opened Aug 5, 2024 by Dolu1990 Loading…
set rst name for default clock domain by ClockDomainConfig
#1484 opened Jul 17, 2024 by yportne13 Loading…
1
RFC: Add blackboxing for simple 1-port synchronous ROMs
#1475 opened Jul 11, 2024 by bunnie Loading…
2 tasks
20
ACE & ACE-Lite support
#1450 opened Jun 12, 2024 by KireinaHoro • Draft
3 of 8 tasks
5
Bugfix/wb pipelined
#1375 opened Mar 26, 2024 by jdavidberger Loading…
1
71
Ability to remap address for BusSlaveFactory
#1354 opened Mar 13, 2024 by KireinaHoro • Draft
2 tasks
14
Verilog generated when using synchronous resets is not understood by SymbiYosys - remove "assert() else begin end"-block generation for now
#1315 opened Feb 19, 2024 by janschiefer Loading…
1
TaggedUnion implementation
#1241 opened Nov 10, 2023 by ronan-lashermes Loading…
2 tasks
35
[feature] FuseSocGeneratorBuilder provide a easy way to use fusesoc
#1232 opened Nov 2, 2023 by chenbo-again Loading…
27
feat: add loadHex function for SparseMemory
#1015 opened Jan 12, 2023 by hanm2019 Loading…
1 of 2 tasks
1
6
Add ethernet udp tx/rx module feature ✨ Feature idea with clear API defined wontfix The issue would not be fixed
#1010 opened Jan 10, 2023 by jjyy-Huang Loading…
1 of 7 tasks
16
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