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  1. Adder-Tree Adder-Tree Public

    Using recursive modules in system verilog to implement a binary adder tree.

    SystemVerilog

  2. MobileNetV1 MobileNetV1 Public

    MobileNetV1 architecture based on CIFAR10 dataset

    Python

  3. lsq-net lsq-net Public

    Forked from zhutmost/lsq-net

    Unofficial implementation of LSQ-Net, a neural network quantization framework

    Python

  4. fmultiplier fmultiplier Public

    Forked from debtanu09/fmultiplier

    This is the verilog implementation of IEEE 754 32 bit floating point multiplier

    Verilog

  5. Floating-Point-Adder Floating-Point-Adder Public

    Forked from shahsaumya00/Floating-Point-Adder

    32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

    Verilog

  6. FloatingPointAdder FloatingPointAdder Public

    Forked from Howeng98/FloatingPointAdder

    floating point adder

    Verilog