gf180 opamp: route the mimcap on the PDK's own layers, and three cell fixes - #110
gf180 opamp: route the mimcap on the PDK's own layers, and three cell fixes#110carloscl03 wants to merge 2 commits into
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Hi @carloscl03 Thanks for the fixes in the cells. This will be very helpful. Just a reminder to update the commit messages to English, and if you have comments in the source code also they should be in English. Thanks, |
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Done. Commit message and source comments are in English. |
Three things kept diff_pair and diff_pair_ibias from matching on gf180.
Pin labels landed off metal. gf180 maps met*_pin and met*_label to the
same non-conducting label layer, and the markers were aligned ('c','b'),
which puts them tangent to the port edge rather than on it. Only VDD1 and
VDD2 extracted, because they happen to sit over drain metal; VTAIL, VN, VP
and B came out as unnamed nets and LVS reported four missing pins.
current_mirror already centres its bulk label for this exact reason.
Dummy source/drain net was chosen by PDK name. The cell routes its dummies
to the tap ring whenever substrate_tap is on, so both extractors put them
on bulk -- the choice follows the layout, not the process. The composite
already had to override it back to 'B', with a comment saying so.
Sub-cell labels leaked into diff_pair_ibias. VTAIL is a top-level pin of a
standalone diff_pair but an internal net there, so the inherited label
extracted as an extra pin. Wrapped the build in a no_pin_labels() context
manager (new in port_utils, replacing the copy-pasted env var dance) and
dropped the cmirror dummies' "HACK ... likely incorrect" PDK check for the
same layout-driven rule.
gf180: LVS 5/8 -> 7/8, DRC 9/9. sky130: no change, LVS 8/8, DRC 9/9.
__add_mimcap_arr hardcoded met4/met5 for the cap plates, which is where
sky130 puts the MIM. On gf180 option A it sits on met2/met3, so the routes
landed two levels above the plates with no via to step down and the whole
compensation array floated -- zero via3 anywhere near it. The layers now
come from pdk.get_grule("capmet"), so both PDKs work.
diff_to_single described an internal node the cell does not build. Its
netlist gave TOP1 and BOT1 a node of their own, V1; in the layout that
node and the output are one net, which the extractor reports with five
terminals. Deleting the whole strip where the two rails overlap still
leaves them connected, so this is the cell's structure rather than a stray
short. VSS2, the counterpart node, already matched on all three terminals.
The comp fill between the centre multipliers used the plusdoped ports,
which are on the implant layer, so at their own width the fill's edges
came out level with the implant instead of inside it: 0.01um of extension
where PP.5b/PP.5dii ask for 0.16. Insetting it by the implant enclosure
clears all eight violations in the opamp and four in the converter, and
still covers the 0.17um comp gap it exists for.
The output stage's well was not tied to its source, and diff_pair_ibias's
pin labels could not be suppressed the way diff_pair's can, so they leaked
into the parent as extra top-level pins.
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The three failing checks were an Rebased onto #103, which is itself now rebased onto current main. Content is unchanged in both, and the only conflict was a comment that this branch shortens. Until #103 merges the diff here shows both changes; it will narrow to this PR's own five files once that one lands. |
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Hi Carlos, Best, |
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there are some merge conflicts. can you please take a look. |
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Please address the CI and conflicts issues. |
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Status update after looking at what rebasing this onto current The pin-label half is superseded. #105 landed The mimcap half needs redoing. #106 rewrote This PR routes to I cannot build gf180 cells on gdstk locally until #102 lands ( The other three fixes here are unaffected: |
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Closing this in favour of #115, which carries the part of it that is still worth having. Both commits on this branch have been overtaken since it was opened: The mimcap routing fix is moot. The complaint was that The pin-label fix is superseded by #105 on That leaves the three cell fixes, which never made it onto this branch and are now #115: the phantom @msaligane — apologies for the delay on the conflict requests. The honest answer turned out to be that there was no conflict worth resolving here, only a PR that had stopped applying. #115 is |
4 participants
Four cell fixes that together take the gf180 opamp to a clean DRC and a
matching netlist. Depends on #103 for
no_pin_labels, which two of these fixes use, andon #108 and #109 for the runner and the mimcap model. The branch is now
stacked on #103, so the diff shows both until that one merges.
The mimcap routing was hardcoded for sky130.
__add_mimcap_arrcarriedthe comment "V2 (cap_metalbottom) is glayout met4, V1 (cap_metaltop) is
met5". True there; on gf180 option A the MIM sits on met2/met3. The routes
landed two levels above the plates with no via to step down, so the whole
compensation cap array was floating --
via3count was zero anywhere nearit. The layers now come from
pdk.get_grule("capmet"), so both PDKs work.diff_to_singledescribed an internal node the cell does not build. Itsnetlist gave TOP1 and BOT1 a node of their own,
V1. In the layout that nodeand the output are one net, which the extractor reports with five terminals.
This is the cell's structure rather than a stray overlap: deleting the entire
strip where the two rails run over each other still leaves them connected,
whereas cutting an accidental short separates the nodes.
VSS2, thecounterpart node, already matched the netlist exactly on all three terminals.
The comp fill between the centre multipliers sat outside the implant. The
gap fill uses the
plusdopedports, which are on the implant layer, so attheir own width the fill's edges came out level with the implant instead of
inside it -- 0.01um of extension where PP.5b/PP.5dii ask for 0.16. Insetting
it by the implant enclosure clears all eight violations in the opamp and the
four in the converter, and still covers the 0.17um comp gap it exists for.
The output stage's well was not tied to its source, and
diff_pair_ibias's pin labels could not be suppressed the waydiff_pair'scan, so they leaked into the parent as extra top-level pins.