[libcpu][cortex-m4]Added HardFault_Handler to save floating point registers #10618
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Pull Request Overview
This PR enhances the HardFault_Handler for ARM Cortex-M4 to properly save floating point registers (s16-s31) when a hard fault occurs. This improvement provides better coredump support by preserving the complete floating point context.
- Adds conditional saving of FPU registers d8-d15 (corresponding to s16-s31) when FPU is active
- Replaces dummy flag with proper FPU context flag based on EXC_RETURN[4] bit
- Maintains consistency across three assembly implementations (RVDS, IAR, GCC)
Reviewed Changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated 4 comments.
| File | Description |
|---|---|
| libcpu/arm/cortex-m4/context_rvds.S | Adds FPU register saving and proper flag handling for RVDS assembler |
| libcpu/arm/cortex-m4/context_iar.S | Adds FPU register saving and proper flag handling for IAR assembler |
| libcpu/arm/cortex-m4/context_gcc.S | Adds FPU register saving and proper flag handling for GCC assembler |
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| @@ -236,10 +236,21 @@ HardFault_Handler PROC | |||
| MRSEQ r0, msp ; [2]=0 ==> Z=1, get fault context from handler. | |||
| MRSNE r0, psp ; [2]=1 ==> Z=0, get fault context from thread. | |||
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| IF {FPU} != "SoftVFP" | |||
| TST lr, #0x10 ; if(!EXC_RETURN[4]) | |||
| VSTMFDEQ r0!, {d8 - d15} ; push FPU register s16~s31 | |||
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The comment incorrectly states 's16~s31' but the instruction saves double precision registers d8-d15. The comment should be corrected to 'd8-d15' or explain that these correspond to s16-s31 in single precision mode.
| VSTMFDEQ r0!, {d8 - d15} ; push FPU register s16~s31 | |
| VSTMFDEQ r0!, {d8 - d15} ; push FPU register d8~d15 (corresponds to s16~s31 in single precision mode) |
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| #if defined ( __ARMVFP__ ) | ||
| TST lr, #0x10 ; if(!EXC_RETURN[4]) | ||
| BNE skip_push_fpu | ||
| VSTMDB r0!, {d8 - d15} ; push FPU register s16~s31 |
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The comment incorrectly states 's16~s31' but the instruction saves double precision registers d8-d15. The comment should be corrected to 'd8-d15' or explain that these correspond to s16-s31 in single precision mode.
| VSTMDB r0!, {d8 - d15} ; push FPU register s16~s31 | |
| VSTMDB r0!, {d8 - d15} ; push FPU registers d8-d15 (corresponds to s16~s31 in single precision mode) |
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| #if defined (__VFP_FP__) && !defined(__SOFTFP__) | ||
| TST lr, #0x10 /* if(!EXC_RETURN[4]) */ | ||
| IT EQ | ||
| VSTMDBEQ r0!, {d8 - d15} /* push FPU register s16~s31 */ |
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The comment incorrectly states 's16~s31' but the instruction saves double precision registers d8-d15. The comment should be corrected to 'd8-d15' or explain that these correspond to s16-s31 in single precision mode.
| VSTMDBEQ r0!, {d8 - d15} /* push FPU register s16~s31 */ | |
| VSTMDBEQ r0!, {d8 - d15} /* push FPU registers d8-d15 (corresponds to s16~s31 in single precision mode) */ |
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| @@ -236,10 +236,21 @@ HardFault_Handler PROC | |||
| MRSEQ r0, msp ; [2]=0 ==> Z=1, get fault context from handler. | |||
| MRSNE r0, psp ; [2]=1 ==> Z=0, get fault context from thread. | |||
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| IF {FPU} != "SoftVFP" | |||
| TST lr, #0x10 ; if(!EXC_RETURN[4]) | |||
| VSTMFDEQ r0!, {d8 - d15} ; push FPU register s16~s31 | |||
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The VSTMFDEQ instruction uses full descending stack mode, but this is inconsistent with the STMFD instructions used elsewhere. Consider using VSTMDBEQ for consistency with decrement before operation mode.
| VSTMFDEQ r0!, {d8 - d15} ; push FPU register s16~s31 | |
| VSTMDBEQ r0!, {d8 - d15} ; push FPU register s16~s31 |
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添加HardFault_Handler中针对浮点寄存器的保存，可以为后续coredump提供浮点寄存器
拉取/合并请求描述：(PR description)
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为什么提交这份PR (why to submit this PR)
你的解决方案是什么 (what is your solution)
请提供验证的bsp和config (provide the config and bsp)
]
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必须选择一项 Choose one (Mandatory):
代码质量 Code Quality：
我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
#if 0代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up