Feat/m1

README.rst

@@ -101,7 +101,7 @@ The usage of OSACA can be listed as:
 --arch ARCH
   needs to be replaced with the target architecture abbreviation.
   Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX``, ``ICL`` (Client), ``ICX`` (Server) for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2``, and ``ZEN3`` for AMD Zen architectures.
-  Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110,  and ``A64FX`` for Fujitsu's HPC ARM architecture are available.
+  Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, ``A64FX`` for Fujitsu's HPC ARM architecture, and ``M1`` for the Apple M1-Firestorm performance core are available.
   If no micro-architecture is given, OSACA assumes a default architecture for x86/AArch64.
 --fixed
   Run the throughput analysis with fixed port utilization for all suitable ports per instruction.

osaca/data/isa/aarch64.yml

@@ -850,7 +850,7 @@ instruction_forms:
           shape: "*"
           source: true
           destination: false
-    - name: ldp
+    - name: [ldp, ldnp]
       operands:
         - class: register
           prefix: "*"
@@ -895,7 +895,7 @@ instruction_forms:
         source: true
         destination: false
       operation: "op1['name'] = op2['name']; op1['value'] = op2['value']"
-    - name: stp
+    - name: [stp, stnp]
       operands:
         - class: register
           prefix: "*"